diff options
author | Ruwen Liu <ot_ruwen.liu@mediatek.com> | 2021-11-04 13:30:23 +0800 |
---|---|---|
committer | Hung-Te Lin <hungte@chromium.org> | 2021-11-08 09:02:47 +0000 |
commit | 0480a19d4c59eb3502b6d12618f437943b163fdf (patch) | |
tree | bedb44f8807300c9d38057ceb01b96ec316e3d1e /src | |
parent | 381860454fb5a1a6ffc4c8d1fdf3f021f75cbcbc (diff) | |
download | coreboot-0480a19d4c59eb3502b6d12618f437943b163fdf.tar.gz coreboot-0480a19d4c59eb3502b6d12618f437943b163fdf.tar.bz2 coreboot-0480a19d4c59eb3502b6d12618f437943b163fdf.zip |
soc/mediatek/mt8186: Add SPI driver support
Add SPI controller drivers.
TEST=build pass
BUG=b:202871018
Signed-off-by: Ruwen Liu <ot_ruwen.liu@mediatek.com>
Change-Id: I59a885c4fa31b6e2921698eaa3b97dbdc3144946
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/soc/mediatek/mt8186/Makefile.inc | 8 | ||||
-rw-r--r-- | src/soc/mediatek/mt8186/include/soc/spi.h | 17 | ||||
-rw-r--r-- | src/soc/mediatek/mt8186/spi.c | 120 |
3 files changed, 140 insertions, 5 deletions
diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index a68d051f1efb..cb07ac05557a 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -6,14 +6,14 @@ bootblock-y += ../common/flash_controller.c bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/pll.c pll.c -bootblock-$(CONFIG_SPI_FLASH) += spi.c +bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c timer.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c wdt.c verstage-y += ../common/flash_controller.c verstage-y += ../common/gpio.c gpio.c -verstage-$(CONFIG_SPI_FLASH) += spi.c +verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c timer.c verstage-y += ../common/uart.c verstage-y += ../common/wdt.c wdt.c @@ -22,7 +22,7 @@ romstage-y += ../common/cbmem.c romstage-y += emi.c romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c -romstage-$(CONFIG_SPI_FLASH) += spi.c +romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c wdt.c @@ -30,7 +30,7 @@ romstage-y += ../common/wdt.c wdt.c ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c -ramstage-$(CONFIG_SPI_FLASH) += spi.c +ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c ramstage-y += ../common/timer.c timer.c ramstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8186/include/soc/spi.h b/src/soc/mediatek/mt8186/include/soc/spi.h index fbf3995b7af0..15e7b9182f33 100644 --- a/src/soc/mediatek/mt8186/include/soc/spi.h +++ b/src/soc/mediatek/mt8186/include/soc/spi.h @@ -8,7 +8,22 @@ #ifndef MTK_MT8186_SPI_H #define MTK_MT8186_SPI_H -#include <spi-generic.h> +#include <soc/spi_common.h> + +#define SPI_BUS_NUMBER 6 + +#define GET_SCK_REG(x) x->spi_cfg2_reg + +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) + +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) + +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) +DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) enum { SPI_NOR_GPIO_SET0 = 0, diff --git a/src/soc/mediatek/mt8186/spi.c b/src/soc/mediatek/mt8186/spi.c index 4a1c13caa562..87f669dc7c10 100644 --- a/src/soc/mediatek/mt8186/spi.c +++ b/src/soc/mediatek/mt8186/spi.c @@ -7,17 +7,116 @@ #include <assert.h> #include <device/mmio.h> +#include <spi_flash.h> #include <soc/addressmap.h> #include <soc/flash_controller_common.h> #include <soc/gpio.h> #include <soc/spi.h> +struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { + { + .regs = (void *)SPI0_BASE, + .cs_gpio = GPIO(SPI0_CSB), + }, + { + .regs = (void *)SPI1_BASE, + .cs_gpio = GPIO(SPI1_CSB), + }, + { + .regs = (void *)SPI2_BASE, + .cs_gpio = GPIO(SPI2_CSB), + }, + { + .regs = (void *)SPI3_BASE, + .cs_gpio = GPIO(SPI3_CSB), + }, + { + .regs = (void *)SPI4_BASE, + .cs_gpio = GPIO(EINT11), + }, + { + .regs = (void *)SPI5_BASE, + .cs_gpio = GPIO(SPI5_CSB), + } +}; + struct pad_func { gpio_t gpio; u8 func; }; #define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} +#define PAD_FUNC_GPIO(name) {GPIO(name), 0} + +static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = { + { + PAD_FUNC(SPI0_MI, SPI0_MI_A), + PAD_FUNC_GPIO(SPI0_CSB), + PAD_FUNC(SPI0_MO, SPI0_MO_A), + PAD_FUNC(SPI0_CLK, SPI0_CLK_A), + }, + { + PAD_FUNC(SPI1_MI, SPI1_MI_A), + PAD_FUNC_GPIO(SPI1_CSB), + PAD_FUNC(SPI1_MO, SPI1_MO_A), + PAD_FUNC(SPI1_CLK, SPI1_CLK_A), + }, + { + PAD_FUNC(SPI2_MI, SPI2_MI_A), + PAD_FUNC_GPIO(SPI2_CSB), + PAD_FUNC(SPI2_MO, SPI2_MO_A), + PAD_FUNC(SPI2_CK, SPI2_CLK_A), + }, + { + PAD_FUNC(SPI3_MI, SPI3_MI), + PAD_FUNC_GPIO(SPI3_CSB), + PAD_FUNC(SPI3_MO, SPI3_MO), + PAD_FUNC(SPI3_CLK, SPI3_CLK), + }, + { + PAD_FUNC(EINT13, SPI4_MI_A), + PAD_FUNC_GPIO(EINT11), + PAD_FUNC(EINT12, SPI4_MO_A), + PAD_FUNC(EINT10, SPI4_CLK_A), + }, + { + PAD_FUNC(SPI5_MI, SPI5_MI), + PAD_FUNC_GPIO(SPI5_CSB), + PAD_FUNC(SPI5_MO, SPI5_MO), + PAD_FUNC(SPI5_CLK, SPI5_CLK), + }, +}; + +static const struct pad_func pad1_funcs[SPI_BUS_NUMBER][4] = { + { + PAD_FUNC(EINT3, SPI0_MI_B), + PAD_FUNC_GPIO(EINT1), + PAD_FUNC(EINT2, SPI0_MO_B), + PAD_FUNC(EINT0, SPI0_CLK_B), + }, + { + PAD_FUNC(EINT9, SPI1_MI_B), + PAD_FUNC_GPIO(EINT7), + PAD_FUNC(EINT8, SPI1_MO_B), + PAD_FUNC(EINT6, SPI1_CLK_B), + }, + { + PAD_FUNC(CAM_PDN1, SPI2_MI_B), + PAD_FUNC_GPIO(CAM_PDN0), + PAD_FUNC(CAM_RST0, SPI2_MO_B), + PAD_FUNC(EINT18, SPI2_CLK_B), + }, + { + }, + { + PAD_FUNC(I2S2_DI, SPI4_MI_B), + PAD_FUNC_GPIO(I2S2_BCK), + PAD_FUNC(I2S2_LRCK, SPI4_MO_B), + PAD_FUNC(I2S2_MCK, SPI4_CLK_B), + }, + { + }, +}; static const struct pad_func nor_pinmux[SPI_NOR_GPIO_SET_NUM][4] = { /* GPIO 36 ~ 39 */ @@ -49,6 +148,22 @@ void mtk_snfc_init(int gpio_set) } } +void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select) +{ + assert(bus < SPI_BUS_NUMBER); + const struct pad_func *ptr; + + if (pad_select == SPI_PAD0_MASK) { + ptr = pad0_funcs[bus]; + } else { + assert((bus == 0 || bus == 1 || bus == 2 || bus == 4) && + pad_select == SPI_PAD1_MASK); + ptr = pad1_funcs[bus]; + } + for (int i = 0; i < 4; i++) + gpio_set_mode(ptr[i].gpio, ptr[i].func); +} + static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, .flash_probe = mtk_spi_flash_probe, @@ -56,6 +171,11 @@ static const struct spi_ctrlr spi_flash_ctrlr = { const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = SPI_BUS_NUMBER - 1, + }, + { .ctrlr = &spi_flash_ctrlr, .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, |