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| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2017-09-16 02:01:13 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-09-21 03:14:54 +0000 |
| commit | 09703f64940a66345f27d28c0e339c7ac1864b54 (patch) | |
| tree | a37b6efec21ef2092daecc67199b9e6fcbf58d62 /src | |
| parent | 03937391bc80613f4591b5f5c0d00d2607406dc2 (diff) | |
| download | coreboot-09703f64940a66345f27d28c0e339c7ac1864b54.tar.gz coreboot-09703f64940a66345f27d28c0e339c7ac1864b54.tar.bz2 coreboot-09703f64940a66345f27d28c0e339c7ac1864b54.zip | |
mb/google/{poppy,soraka}: Enable LTR for Root port
Enable LTR for Root port 0, where wifi card is connected.
BUG=b:65570878
TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported
by AER driver for root port 0.
Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajat Jain <rajatja@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/google/poppy/variants/soraka/devicetree.cb | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 0bd2efc92c91..61b16e65f1d2 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -153,7 +153,9 @@ chip soc/intel/skylake # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" # RP 1, Enable Advanced Error Reporting - register PcieRpAdvancedErrorReporting[0] = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + # RP 1, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[0]" = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index ee9c5b778003..fa16ae02e561 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -153,7 +153,9 @@ chip soc/intel/skylake # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" # RP 1, Enable Advanced Error Reporting - register PcieRpAdvancedErrorReporting[0] = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + # RP 1, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[0]" = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port |