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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-05-25 21:07:23 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-27 16:43:15 +0000 |
| commit | 0fec867e32a2df821e5a3569496b1dda7a2b1d5f (patch) | |
| tree | 12afe2c83c20619b3a6af93dfa4425969475ecc0 /src | |
| parent | 6a936fc6ae0ba825f5830c072007c05db4242691 (diff) | |
| download | coreboot-0fec867e32a2df821e5a3569496b1dda7a2b1d5f.tar.gz coreboot-0fec867e32a2df821e5a3569496b1dda7a2b1d5f.tar.bz2 coreboot-0fec867e32a2df821e5a3569496b1dda7a2b1d5f.zip | |
soc/amd/picasso: add devicetree setting for PSPP policy
Since the default for the corresponding UPD of the Picasso FSP is
DXIO_PSPP_POWERSAVE and the devicetree default is DXIO_PSPP_PERFORMANCE,
add a deviectree setting for each board that's using the Picasso SoC
code to not change the setting for the existing boards.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src')
7 files changed, 20 insertions, 0 deletions
diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index a3385b92be57..7797c3e44d44 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -136,6 +136,8 @@ chip soc/amd/picasso register "gpp_clk_config[5]" = "GPP_CLK_REQ" register "gpp_clk_config[6]" = "GPP_CLK_REQ" + register "pspp_policy" = "DXIO_PSPP_POWERSAVE" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb index ee0af53da2ce..9a3e78ec6e2f 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -136,6 +136,8 @@ chip soc/amd/picasso register "gpp_clk_config[5]" = "GPP_CLK_OFF" register "gpp_clk_config[6]" = "GPP_CLK_OFF" + register "pspp_policy" = "DXIO_PSPP_POWERSAVE" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 994c9106abcf..826a84bd3015 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -136,6 +136,8 @@ chip soc/amd/picasso register "gpp_clk_config[5]" = "GPP_CLK_REQ" register "gpp_clk_config[6]" = "GPP_CLK_REQ" + register "pspp_policy" = "DXIO_PSPP_POWERSAVE" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index a8c270e5fee5..252540093c80 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -250,6 +250,8 @@ chip soc/amd/picasso register "gpp_clk_config[5]" = "GPP_CLK_OFF" register "gpp_clk_config[6]" = "GPP_CLK_OFF" + register "pspp_policy" = "DXIO_PSPP_POWERSAVE" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 840dfe7f113d..89bca93d1734 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -243,6 +243,8 @@ chip soc/amd/picasso register "gpp_clk_config[5]" = "GPP_CLK_OFF" register "gpp_clk_config[6]" = "GPP_CLK_OFF" + register "pspp_policy" = "DXIO_PSPP_POWERSAVE" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 359fa956f82e..4c43b1fdffdd 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -263,6 +263,13 @@ struct soc_amd_picasso_config { GPP_CLK_OFF, /* GPP clk off */ } gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; + /* performance policy for the PCIe links: power consumption vs. link speed */ + enum { + DXIO_PSPP_PERFORMANCE = 0, + DXIO_PSPP_BALANCED, + DXIO_PSPP_POWERSAVE, + } pspp_policy; + /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */ bool acp_i2s_use_external_48mhz_osc; diff --git a/src/soc/amd/picasso/fsp_m_params.c b/src/soc/amd/picasso/fsp_m_params.c index f196e48f1209..3532fb2c2c42 100644 --- a/src/soc/amd/picasso/fsp_m_params.c +++ b/src/soc/amd/picasso/fsp_m_params.c @@ -112,5 +112,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->sata_enable = devtree_sata_dev_enabled(); mcfg->hdmi2_disable = config->hdmi2_disable; + /* PCIe power vs. speed */ + mcfg->pspp_policy = config->pspp_policy; + mainboard_updm_update(mcfg); } |