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| author | Jenny TC <jenny.tc@intel.com> | 2015-06-18 14:55:10 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-29 19:26:14 +0200 |
| commit | 153ae105e5c928982b50d1599e626ae6ff494824 (patch) | |
| tree | ccf66bb87cbd2b6e74fdc111911733ce6a7d4f0e /src | |
| parent | 556538af85fc1d6387e8af86fae67e26b0524d63 (diff) | |
| download | coreboot-153ae105e5c928982b50d1599e626ae6ff494824.tar.gz coreboot-153ae105e5c928982b50d1599e626ae6ff494824.tar.bz2 coreboot-153ae105e5c928982b50d1599e626ae6ff494824.zip | |
BCRD2: Enable PMIC SVID config
Enable PMIC SVID config for BCRD2 based
on board id. UPD parameter is used to
select the SVID config and PMIC I2C bus
number
BRANCH=None
BUG=None
TEST=Build and boot the system
Change-Id: I3c4c06bd25c241abdf46aa14af74eecf77cf77a6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 10bb8d4ad96d1187f6e135ca1535d70ae45ee887
Original-Change-Id: I9191db7bace4f4840e3c32381093c6c0806f7c32
Original-Signed-off-by: Jenny TC <jenny.tc@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/282156
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11060
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/braswell/chip.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index d70aa9b1174e..7422bc4c09b8 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -30,8 +30,9 @@ #include <fsp_util.h> #include <soc/pci_devs.h> -#define SVID_CONFIG1 1 -#define SVID_CONFIG3 3 +#define SVID_CONFIG1 1 +#define SVID_CONFIG3 3 +#define SVID_PMIC_CONFIG 8 struct soc_intel_braswell_config { uint8_t enable_xdp_tap; |