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| author | John Su <john_su@compal.corp-partner.google.com> | 2022-09-28 10:25:30 +0800 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-10-06 18:27:54 +0000 |
| commit | 153e526f779323646225554f2643f8309743a0a7 (patch) | |
| tree | 55ad70fd1e743078a8ee7e3e8da9c2e12d0a6d90 /src | |
| parent | 4531edf083b86e350bbb9e108e410158c8eeea94 (diff) | |
| download | coreboot-153e526f779323646225554f2643f8309743a0a7.tar.gz coreboot-153e526f779323646225554f2643f8309743a0a7.tar.bz2 coreboot-153e526f779323646225554f2643f8309743a0a7.zip | |
mb/google/brya/var/mithrax: adjust I2C5 times for TP
This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C5 to
follow I2C specification.
I2C_TCHPAD_SCL high period time is from 0.53 us to 0.6952 us.
I2C_TCHPAD_SDA hold time is from 0.13 us to 0.4623 us.
BUG=b:249031186
BRANCH=brya
TEST=EE check OK with test FW and TP function is normal.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I5977f0dbba8924cc8a1c72c36358d6ba6f2de940
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67920
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/mithrax/overridetree.cb | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb index 589953506be9..2755c704cfd4 100644 --- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb @@ -81,7 +81,12 @@ chip soc/intel/alderlake .speed = I2C_SPEED_FAST, .rise_time_ns = 550, .fall_time_ns = 400, - .data_hold_time_ns = 50, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 160, + .scl_hcnt = 70, + .sda_hold = 40, + } }, }" |