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| author | Varshit Pandya <pandyavarshit@gmail.com> | 2024-02-22 20:37:17 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-24 19:27:37 +0000 |
| commit | 15d55439dabafd8d4d874b818234d3859fda7d4c (patch) | |
| tree | fc2449ed940a5dadcc962ba9550024001680c897 /src | |
| parent | a99b580c75278d306d2d1eb0b6893e83388ec513 (diff) | |
| download | coreboot-15d55439dabafd8d4d874b818234d3859fda7d4c.tar.gz coreboot-15d55439dabafd8d4d874b818234d3859fda7d4c.tar.bz2 coreboot-15d55439dabafd8d4d874b818234d3859fda7d4c.zip | |
soc/amd/glinda: Update GPP_CLK_OUTPUT_AVAILABLE to 7
Glinda started as a copy of mendocino and GPP_CLK_OUTPUT_AVAILABLE was
not updated. GPP_CLK_OUTPUT_AVAILABLE should be 7 as per Processor
Programming Reference (PPR) (#57254), table "GPP ClkREQB Mapping".
Change-Id: I26e9dea58b2ddf5cbedbcccb8bcbc5f9efab3165
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80701
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/glinda/include/soc/southbridge.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/glinda/include/soc/southbridge.h b/src/soc/amd/glinda/include/soc/southbridge.h index 9cd835b21a60..b7ac8a8509da 100644 --- a/src/soc/amd/glinda/include/soc/southbridge.h +++ b/src/soc/amd/glinda/include/soc/southbridge.h @@ -87,7 +87,7 @@ #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ /* FCH MISC Registers 0xfed80e00 */ -#define GPP_CLK_OUTPUT_AVAILABLE 4 +#define GPP_CLK_OUTPUT_AVAILABLE 7 #define MISC_CLKGATEDCNTL 0x2c #define ALINKCLK_GATEOFFEN BIT(16) |