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| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-11 10:39:20 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-23 12:43:26 +0000 |
| commit | 16c06c273cf88a7fa837bbaa72392872d691f795 (patch) | |
| tree | a3ecb2a515e100232caf14a6f0e136dda355f2e8 /src | |
| parent | b3aaa63e8f99bb9ae32d08136f59a72d3b97de10 (diff) | |
| download | coreboot-16c06c273cf88a7fa837bbaa72392872d691f795.tar.gz coreboot-16c06c273cf88a7fa837bbaa72392872d691f795.tar.bz2 coreboot-16c06c273cf88a7fa837bbaa72392872d691f795.zip | |
soc/intel/cannonlake: Add ICC limits for CFL-S DT 4
TEST=Boot with an i3-9100F and see no vr_config errors.
Change-Id: Ic62ef038ad11d147a38804f694d3e056611b96db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47445
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/vr_config.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 2b621f7763fb..1f855887daff 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -206,6 +206,11 @@ VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2) { { 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 58, 45, 45) }, { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 40, 35, 35) }, }; +VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4) { + { 71, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 100, 45, 45) }, + { 62, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 79, 45, 45) }, + { 35, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 66, 35, 35) }, +}; VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8) { { 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) }, { 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 186, 45, 45) }, @@ -304,6 +309,7 @@ static const struct vr_lookup vr_config_icc[] = { VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H), VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H_4), VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2), + VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4), VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8), VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8), VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8), |