src/*/post_code.h: Change post code prefix to POSTCODE

The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.

The files was changed by running the following bash script from the
top level directory.

header="src/soc/amd/common/block/include/amdblocks/post_codes.h \
	src/include/cpu/intel/post_codes.h \
	src/soc/intel/common/block/include/intelblocks/post_codes.h"

array=`grep -r "#define POST_" $header | \
	tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2`

for str in $array; do
	splitstr=`echo $str | cut -d '_' -f2-`
	grep -r $str src | cut -d ':' -f 1 | \
		xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g"
done

Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad
Signed-off-by: Yuchen He <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

23 files changed, 159 insertions, 159 deletions

diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
index 316b703271cf..9c60308b2866 100644
--- a/src/cpu/intel/car/core2/cache_as_ram.S
+++ b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -29,7 +29,7 @@ wait_for_sipi:
 	bt	$12, %eax
 	jc	wait_for_sipi
 
-	post_code(POST_SOC_CLEAR_FIXED_MTRRS)
+	post_code(POSTCODE_SOC_CLEAR_FIXED_MTRRS)
 
 	/* Clear/disable fixed MTRRs */
 	mov	$fixed_mtrr_list, %ebx
@@ -59,7 +59,7 @@ clear_var_mtrr:
 	dec	%ebx
 	jnz	clear_var_mtrr
 
-	post_code(POST_SOC_SET_DEF_MTRR_TYPE)
+	post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE)
 	/* Configure the default memory type to uncacheable. */
 	movl	$MTRR_DEF_TYPE_MSR, %ecx
 	rdmsr
@@ -84,7 +84,7 @@ addrsize_set_high:
 	movl	$MTRR_PHYS_MASK(1), %ecx
 	wrmsr
 
-	post_code(POST_SOC_SET_MTRR_BASE)
+	post_code(POSTCODE_SOC_SET_MTRR_BASE)
 	/* Set Cache-as-RAM base address. */
 	movl	$(MTRR_PHYS_BASE(0)), %ecx
 	movl	$_car_mtrr_start, %eax
@@ -92,7 +92,7 @@ addrsize_set_high:
 	xorl	%edx, %edx
 	wrmsr
 
-	post_code(POST_SOC_SET_MTRR_MASK)
+	post_code(POSTCODE_SOC_SET_MTRR_MASK)
 	/* Set Cache-as-RAM mask. */
 	movl	$(MTRR_PHYS_MASK(0)), %ecx
 	rdmsr
@@ -100,7 +100,7 @@ addrsize_set_high:
 	orl	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
 
-	post_code(POST_SOC_ENABLE_MTRRS)
+	post_code(POSTCODE_SOC_ENABLE_MTRRS)
 
 	/* Enable MTRR. */
 	movl	$MTRR_DEF_TYPE_MSR, %ecx
@@ -128,7 +128,7 @@ addrsize_set_high:
 	shr	$2, %ecx
 	rep	stosl
 
-	post_code(POST_SOC_DISABLE_CACHE)
+	post_code(POSTCODE_SOC_DISABLE_CACHE)
 	/* Enable Cache-as-RAM mode by disabling cache. */
 	movl	%cr0, %eax
 	orl	$CR0_CacheDisable, %eax
@@ -147,7 +147,7 @@ addrsize_set_high:
 	orl	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
 
-	post_code(POST_SOC_ENABLE_CACHE)
+	post_code(POSTCODE_SOC_ENABLE_CACHE)
 	/* Enable cache. */
 	movl	%cr0, %eax
 	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
@@ -181,7 +181,7 @@ addrsize_set_high:
 #endif
 
 before_c_entry:
-	post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY)
+	post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY)
 	call	bootblock_c_entry_bist
 
 	/* Should never see this postcode */
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index 187b1ca9e2cc..18ac07036eb7 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -34,14 +34,14 @@ wait_for_sipi:
 	bt	$12, %eax
 	jc	wait_for_sipi
 
-	post_code(POST_SOC_SET_DEF_MTRR_TYPE)
+	post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE)
 	/* Clean-up MTRR_DEF_TYPE_MSR. */
 	movl	$MTRR_DEF_TYPE_MSR, %ecx
 	xorl	%eax, %eax
 	xorl	%edx, %edx
 	wrmsr
 
-	post_code(POST_SOC_CLEAR_FIXED_MTRRS)
+	post_code(POSTCODE_SOC_CLEAR_FIXED_MTRRS)
 	/* Clear/disable fixed MTRRs */
 	mov	$fixed_mtrr_list, %ebx
 	xor	%eax, %eax
@@ -88,7 +88,7 @@ addrsize_set_high:
 	movl	$MTRR_PHYS_MASK(1), %ecx
 	wrmsr
 
-	post_code(POST_SOC_SET_MTRR_BASE)
+	post_code(POSTCODE_SOC_SET_MTRR_BASE)
 	/* Set Cache-as-RAM base address. */
 	movl	$(MTRR_PHYS_BASE(0)), %ecx
 	movl	car_mtrr_start, %eax
@@ -96,7 +96,7 @@ addrsize_set_high:
 	xorl	%edx, %edx
 	wrmsr
 
-	post_code(POST_SOC_SET_MTRR_MASK)
+	post_code(POSTCODE_SOC_SET_MTRR_MASK)
 	/* Set Cache-as-RAM mask. */
 	movl	$(MTRR_PHYS_MASK(0)), %ecx
 	rdmsr
@@ -117,7 +117,7 @@ addrsize_set_high:
 	orl	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
 
-	post_code(POST_SOC_ENABLE_MTRRS)
+	post_code(POSTCODE_SOC_ENABLE_MTRRS)
 
 	/* Enable MTRR. */
 	movl	$MTRR_DEF_TYPE_MSR, %ecx
@@ -188,7 +188,7 @@ end_microcode_update:
 	orl	$3, %eax
 	wrmsr
 
-	post_code(POST_SOC_DISABLE_CACHE)
+	post_code(POSTCODE_SOC_DISABLE_CACHE)
 	/* Enable Cache-as-RAM mode by disabling cache. */
 	movl	%cr0, %eax
 	orl	$CR0_CacheDisable, %eax
@@ -199,7 +199,7 @@ end_microcode_update:
 	orl	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
 
-	post_code(POST_SOC_ENABLE_CACHE)
+	post_code(POSTCODE_SOC_ENABLE_CACHE)
 	/* Enable cache. */
 	movl	%cr0, %eax
 	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
@@ -234,7 +234,7 @@ end_microcode_update:
 #endif
 
 before_c_entry:
-	post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY)
+	post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY)
 	call	bootblock_c_entry_bist
 
 	/* Should never see this postcode */
diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S
index 56370f88412e..9e37b4644c29 100644
--- a/src/cpu/intel/car/non-evict/exit_car.S
+++ b/src/cpu/intel/car/non-evict/exit_car.S
@@ -13,14 +13,14 @@
 chipset_teardown_car:
 	pop %esp
 
-	post_code(POST_POSTCAR_DISABLE_CACHE)
+	post_code(POSTCODE_POSTCAR_DISABLE_CACHE)
 
 	/* Disable cache. */
 	movl	%cr0, %eax
 	orl	$CR0_CacheDisable, %eax
 	movl	%eax, %cr0
 
-	post_code(POST_POSTCAR_DISABLE_DEF_MTRR)
+	post_code(POSTCODE_POSTCAR_DISABLE_DEF_MTRR)
 
 	/* Disable MTRR. */
 	movl	$MTRR_DEF_TYPE_MSR, %ecx
@@ -36,7 +36,7 @@ chipset_teardown_car:
 	andl	$~1, %eax
 	wrmsr
 
-	post_code(POST_POSTCAR_TEARDOWN_DONE)
+	post_code(POSTCODE_POSTCAR_TEARDOWN_DONE)
 
 	/* Return to caller. */
 	jmp	*%esp
diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S
index 1431d323e6f6..779dbcca8a01 100644
--- a/src/cpu/intel/car/p3/cache_as_ram.S
+++ b/src/cpu/intel/car/p3/cache_as_ram.S
@@ -42,7 +42,7 @@ clear_var_mtrr:
 	inc	%ecx
 	dec	%ebx
 	jnz	clear_var_mtrr
-	post_code(POST_SOC_SET_DEF_MTRR_TYPE)
+	post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE)
 
 	/* Configure the default memory type to uncacheable. */
 	movl	$MTRR_DEF_TYPE_MSR, %ecx
@@ -50,7 +50,7 @@ clear_var_mtrr:
 	andl	$(~0x00000cff), %eax
 	wrmsr
 
-	post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS)
+	post_code(POSTCODE_SOC_DETERMINE_CPU_ADDR_BITS)
 
 	/* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */
 	movl	$1, %eax
@@ -68,7 +68,7 @@ addrsize_set_high:
 	movl	$MTRR_PHYS_MASK(1), %ecx
 	wrmsr
 
-	post_code(POST_SOC_SET_CAR_BASE)
+	post_code(POSTCODE_SOC_SET_CAR_BASE)
 
 	/* Set Cache-as-RAM base address. */
 	movl	$(MTRR_PHYS_BASE(0)), %ecx
@@ -84,7 +84,7 @@ addrsize_set_high:
 	orl	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
 
-	post_code(POST_SOC_ENABLE_MTRRS)
+	post_code(POSTCODE_SOC_ENABLE_MTRRS)
 
 	/* Enable MTRR. */
 	movl	$MTRR_DEF_TYPE_MSR, %ecx
@@ -92,7 +92,7 @@ addrsize_set_high:
 	orl	$MTRR_DEF_TYPE_EN, %eax
 	wrmsr
 
-	post_code(POST_SOC_ENABLE_CACHE)
+	post_code(POSTCODE_SOC_ENABLE_CACHE)
 
 	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
 	movl	%cr0, %eax
@@ -114,7 +114,7 @@ addrsize_set_high:
 	xorl	%eax, %eax
 	rep	stosl
 
-	post_code(POST_SOC_DISABLE_CACHE)
+	post_code(POSTCODE_SOC_DISABLE_CACHE)
 	/* Enable Cache-as-RAM mode by disabling cache. */
 	movl	%cr0, %eax
 	orl	$CR0_CacheDisable, %eax
@@ -133,7 +133,7 @@ addrsize_set_high:
 	orl	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
 
-	post_code(POST_SOC_FILL_CACHE)
+	post_code(POSTCODE_SOC_FILL_CACHE)
 	/* Enable cache. */
 	movl	%cr0, %eax
 	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
@@ -156,7 +156,7 @@ addrsize_set_high:
 	pushl	%eax	/* tsc[31:0] */
 
 before_c_entry:
-	post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY)
+	post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY)
 	call	bootblock_c_entry_bist
 
 	/* Should never see this postcode */
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 0362d104fa8b..9f514ef59260 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -54,7 +54,7 @@ clear_var_mtrr:
 	inc	%ecx
 	dec	%ebx
 	jnz	clear_var_mtrr
-	post_code(POST_SOC_SET_DEF_MTRR_TYPE)
+	post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE)
 
 	/* Configure the default memory type to uncacheable. */
 	movl	$MTRR_DEF_TYPE_MSR, %ecx
@@ -62,7 +62,7 @@ clear_var_mtrr:
 	andl	$(~0x00000cff), %eax
 	wrmsr
 
-	post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS)
+	post_code(POSTCODE_SOC_DETERMINE_CPU_ADDR_BITS)
 
 	/* Determine CPU_ADDR_BITS and load PHYSMASK high
 	 * word to %edx.
@@ -106,7 +106,7 @@ addrsize_set_high:
 
 bsp_init:
 
-	post_code(POST_SOC_BSP_INIT)
+	post_code(POSTCODE_SOC_BSP_INIT)
 
 	/* Send INIT IPI to all excluding ourself. */
 	movl	LAPIC(ICR), %edi
@@ -120,7 +120,7 @@ bsp_init:
 	andl	$LAPIC_ICR_BUSY, %ecx
 	jnz	1b
 
-	post_code(POST_SOC_COUNT_CORES)
+	post_code(POSTCODE_SOC_COUNT_CORES)
 
 	movl	$1, %eax
 	cpuid
@@ -155,7 +155,7 @@ cores_counted:
 
 hyper_threading_cpu:
 
-	post_code(POST_SOC_CPU_HYPER_THREADING)
+	post_code(POSTCODE_SOC_CPU_HYPER_THREADING)
 
 	/* Send Start IPI to all excluding ourself. */
 	movl	LAPIC(ICR), %edi
@@ -170,7 +170,7 @@ hyper_threading_cpu:
 	andl	$LAPIC_ICR_BUSY, %ecx
 	jnz	1b
 
-	post_code(POST_SOC_CPU_SIBLING_DELAY)
+	post_code(POSTCODE_SOC_CPU_SIBLING_DELAY)
 
 	/* Wait for sibling CPU to start. */
 1:	movl	$(MTRR_PHYS_BASE(0)), %ecx
@@ -186,14 +186,14 @@ hyper_threading_cpu:
 
 
 ap_init:
-	post_code(POST_SOC_CPU_AP_INIT)
+	post_code(POSTCODE_SOC_CPU_AP_INIT)
 
 	/* Do not disable cache (so BSP can enable it). */
 	movl	%cr0, %eax
 	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
 	movl	%eax, %cr0
 
-	post_code(POST_SOC_SET_MTRR_BASE)
+	post_code(POSTCODE_SOC_SET_MTRR_BASE)
 
 	/* MTRR registers are shared between HT siblings. */
 	movl	$(MTRR_PHYS_BASE(0)), %ecx
@@ -201,7 +201,7 @@ ap_init:
 	xorl	%edx, %edx
 	wrmsr
 
-	post_code(POST_SOC_AP_HALT)
+	post_code(POSTCODE_SOC_AP_HALT)
 
 ap_halt:
 	cli
@@ -212,7 +212,7 @@ ap_halt:
 
 sipi_complete:
 
-	post_code(POST_SOC_SET_CAR_BASE)
+	post_code(POSTCODE_SOC_SET_CAR_BASE)
 
 	/* Set Cache-as-RAM base address. */
 	movl	$(MTRR_PHYS_BASE(0)), %ecx
@@ -228,7 +228,7 @@ sipi_complete:
 	orl	$MTRR_PHYS_MASK_VALID, %eax
 	wrmsr
 
-	post_code(POST_SOC_ENABLE_MTRRS)
+	post_code(POSTCODE_SOC_ENABLE_MTRRS)
 
 	/* Enable MTRR. */
 	movl	$MTRR_DEF_TYPE_MSR, %ecx
@@ -271,7 +271,7 @@ has_msr_11e:
 	wrmsr
 no_msr_11e:
 
-	post_code(POST_SOC_ENABLE_CACHE)
+	post_code(POSTCODE_SOC_ENABLE_CACHE)
 
 	/* Cache the whole rom to fetch microcode updates */
 	movl	$MTRR_PHYS_BASE(1), %ecx
@@ -298,7 +298,7 @@ no_msr_11e:
 	jmp	update_bsp_microcode
 	end_microcode_update:
 #endif
-	post_code(POST_SOC_DISABLE_CACHE)
+	post_code(POSTCODE_SOC_DISABLE_CACHE)
 	/* Disable caching to change MTRR's. */
 	movl	%cr0, %eax
 	orl	$CR0_CacheDisable, %eax
@@ -338,7 +338,7 @@ cache_rom:
 	wrmsr
 
 fill_cache:
-	post_code(POST_SOC_FILL_CACHE)
+	post_code(POSTCODE_SOC_FILL_CACHE)
 	/* Enable cache. */
 	movl	%cr0, %eax
 	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
@@ -381,7 +381,7 @@ fill_cache:
 #endif
 
 before_c_entry:
-	post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY)
+	post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY)
 	call	bootblock_c_entry_bist
 
 	/* Should never see this postcode */
diff --git a/src/cpu/intel/car/p4-netburst/exit_car.S b/src/cpu/intel/car/p4-netburst/exit_car.S
index 1684407e81cb..05f77516c3f4 100644
--- a/src/cpu/intel/car/p4-netburst/exit_car.S
+++ b/src/cpu/intel/car/p4-netburst/exit_car.S
@@ -11,14 +11,14 @@
 chipset_teardown_car:
 	pop %esp
 
-	post_code(POST_POSTCAR_DISABLE_CACHE)
+	post_code(POSTCODE_POSTCAR_DISABLE_CACHE)
 
 	/* Disable cache. */
 	movl	%cr0, %eax
 	orl	$CR0_CacheDisable, %eax
 	movl	%eax, %cr0
 
-	post_code(POST_POSTCAR_DISABLE_DEF_MTRR)
+	post_code(POSTCODE_POSTCAR_DISABLE_DEF_MTRR)
 
 	/* Disable MTRR. */
 	movl	$MTRR_DEF_TYPE_MSR, %ecx
@@ -26,7 +26,7 @@ chipset_teardown_car:
 	andl	$(~MTRR_DEF_TYPE_EN), %eax
 	wrmsr
 
-	post_code(POST_POSTCAR_TEARDOWN_DONE)
+	post_code(POSTCODE_POSTCAR_TEARDOWN_DONE)
 
 	/* Return to caller. */
 	jmp	*%esp
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
index 9fd1a0aba27a..5e77263c9711 100644
--- a/src/drivers/amd/agesa/cache_as_ram.S
+++ b/src/drivers/amd/agesa/cache_as_ram.S
@@ -31,7 +31,7 @@ _cache_as_ram_setup:
  */
 bootblock_pre_c_entry:
 
-	post_code(POST_BOOTBLOCK_PRE_C_ENTRY)
+	post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY)
 
 	AMD_ENABLE_STACK
 
@@ -57,7 +57,7 @@ bootblock_pre_c_entry:
 	movd	%mm1, %eax
 	pushl	%eax		/* tsc[31:0] */
 
-	post_code(POST_BOOTBLOCK_PRE_C_DONE)
+	post_code(POSTCODE_BOOTBLOCK_PRE_C_DONE)
 
 	call	bootblock_c_entry
 
diff --git a/src/include/cpu/intel/post_codes.h b/src/include/cpu/intel/post_codes.h
index 6c1ca79f205a..adca9167ad5d 100644
--- a/src/include/cpu/intel/post_codes.h
+++ b/src/include/cpu/intel/post_codes.h
@@ -3,26 +3,26 @@
 #ifndef CPU_INTEL_CAR_POST_CODES_H
 #define CPU_INTEL_CAR_POST_CODES_H
 
-#define POST_SOC_SET_DEF_MTRR_TYPE			0x21
-#define POST_SOC_CLEAR_FIXED_MTRRS			0x22	// Intentional Duplicate
-#define POST_SOC_DETERMINE_CPU_ADDR_BITS		0x22
-#define POST_SOC_BSP_INIT				0x23
-#define POST_SOC_COUNT_CORES				0x24
-#define POST_SOC_CPU_HYPER_THREADING			0x25
-#define POST_SOC_CPU_SIBLING_DELAY			0x26
-#define POST_SOC_CPU_AP_INIT				0x27
-#define POST_SOC_SET_MTRR_BASE				0x28
-#define POST_SOC_SET_MTRR_MASK				0x29	// Intentional Duplicate
-#define POST_SOC_AP_HALT				0x29
-#define POST_SOC_SET_CAR_BASE				0x2a
-#define POST_SOC_ENABLE_MTRRS				0x2b
-#define POST_SOC_ENABLE_CACHE				0x2c
-#define POST_SOC_DISABLE_CACHE				0x2d
-#define POST_SOC_FILL_CACHE				0x2e
-#define POST_BOOTBLOCK_BEFORE_C_ENTRY			0x2f
+#define POSTCODE_SOC_SET_DEF_MTRR_TYPE			0x21
+#define POSTCODE_SOC_CLEAR_FIXED_MTRRS			0x22	// Intentional Duplicate
+#define POSTCODE_SOC_DETERMINE_CPU_ADDR_BITS		0x22
+#define POSTCODE_SOC_BSP_INIT				0x23
+#define POSTCODE_SOC_COUNT_CORES			0x24
+#define POSTCODE_SOC_CPU_HYPER_THREADING		0x25
+#define POSTCODE_SOC_CPU_SIBLING_DELAY			0x26
+#define POSTCODE_SOC_CPU_AP_INIT			0x27
+#define POSTCODE_SOC_SET_MTRR_BASE			0x28
+#define POSTCODE_SOC_SET_MTRR_MASK			0x29	// Intentional Duplicate
+#define POSTCODE_SOC_AP_HALT				0x29
+#define POSTCODE_SOC_SET_CAR_BASE			0x2a
+#define POSTCODE_SOC_ENABLE_MTRRS			0x2b
+#define POSTCODE_SOC_ENABLE_CACHE			0x2c
+#define POSTCODE_SOC_DISABLE_CACHE			0x2d
+#define POSTCODE_SOC_FILL_CACHE				0x2e
+#define POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY		0x2f
 
-#define POST_POSTCAR_DISABLE_CACHE			0x30
-#define POST_POSTCAR_DISABLE_DEF_MTRR			0x31
-#define POST_POSTCAR_TEARDOWN_DONE			0x32
+#define POSTCODE_POSTCAR_DISABLE_CACHE			0x30
+#define POSTCODE_POSTCAR_DISABLE_DEF_MTRR		0x31
+#define POSTCODE_POSTCAR_TEARDOWN_DONE			0x32
 
 #endif
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 2bf5e230c905..63a6b07dc632 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -13,7 +13,7 @@
 
 void __noreturn romstage_main(void)
 {
-	post_code(POST_ROMSTAGE_MAIN);
+	post_code(POSTCODE_ROMSTAGE_MAIN);
 
 	/* Snapshot chipset state prior to any FSP call */
 	fill_chipset_state();
diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
index 372f51517b19..2bd3f5061e0a 100644
--- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
@@ -28,7 +28,7 @@ _cache_as_ram_setup:
 .global bootblock_pre_c_entry
 bootblock_pre_c_entry:
 
-	post_code(POST_BOOTBLOCK_PRE_C_ENTRY)
+	post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY)
 
 	AMD_ENABLE_STACK
 
@@ -42,7 +42,7 @@ bootblock_pre_c_entry:
 	pushl	%eax		/* tsc[31:0] */
 
 before_carstage:
-	post_code(POST_BOOTBLOCK_PRE_C_DONE)
+	post_code(POSTCODE_BOOTBLOCK_PRE_C_DONE)
 
 	call	bootblock_c_entry
 	/* Never reached */
diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S
index 72d778886ace..eb556fabd0a7 100644
--- a/src/soc/amd/common/block/cpu/noncar/pre_c.S
+++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S
@@ -7,7 +7,7 @@
 
 .global bootblock_resume_entry
 bootblock_resume_entry:
-	post_code(POST_BOOTBLOCK_RESUME_ENTRY)
+	post_code(POSTCODE_BOOTBLOCK_RESUME_ENTRY)
 
 	/* Get an early timestamp */
 	rdtsc
@@ -24,7 +24,7 @@ bootblock_resume_entry:
 
 .global bootblock_pre_c_entry
 bootblock_pre_c_entry:
-	post_code(POST_BOOTBLOCK_PRE_C_ENTRY)
+	post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY)
 
 #if ENV_X86_64
 	#include <cpu/x86/64bit/entry64.inc>
@@ -57,7 +57,7 @@ bootblock_pre_c_entry:
 	pushl	%eax		/* tsc[31:0] */
 #endif
 
-	post_code(POST_BOOTBLOCK_PRE_C_DONE)
+	post_code(POSTCODE_BOOTBLOCK_PRE_C_DONE)
 
 	call	bootblock_c_entry
 	/* Never reached */
diff --git a/src/soc/amd/common/block/include/amdblocks/post_codes.h b/src/soc/amd/common/block/include/amdblocks/post_codes.h
index 5251769731b7..10056e7b0a47 100644
--- a/src/soc/amd/common/block/include/amdblocks/post_codes.h
+++ b/src/soc/amd/common/block/include/amdblocks/post_codes.h
@@ -3,31 +3,31 @@
 #ifndef AMD_BLOCK_POST_CODES_H
 #define AMD_BLOCK_POST_CODES_H
 
-#define POST_AGESA_AMDINITRESET			0x37
-#define POST_AGESA_AMDINITEARLY			0x38
+#define POSTCODE_AGESA_AMDINITRESET			0x37
+#define POSTCODE_AGESA_AMDINITEARLY			0x38
 
-#define POST_ROMSTAGE_MAIN			0x40
+#define POSTCODE_ROMSTAGE_MAIN				0x40
 
-#define POST_AGESA_AMDINITPOST			0x40
-#define POST_AGESA_AMDINITPOST_DONE		0x41
+#define POSTCODE_AGESA_AMDINITPOST			0x40
+#define POSTCODE_AGESA_AMDINITPOST_DONE			0x41
 
-#define POST_PSP_NOTIFY_DRAM			0x42
-#define POST_PSP_NOTIFY_DRAM_DONE		0x43
+#define POSTCODE_PSP_NOTIFY_DRAM			0x42
+#define POSTCODE_PSP_NOTIFY_DRAM_DONE			0x43
 
-#define POST_ROMSTAGE_RUN_POSTCAR		0x44
+#define POSTCODE_ROMSTAGE_RUN_POSTCAR			0x44
 
-#define POST_PSP_LOAD_SMU			0x46
-#define POST_AGESA_AMDINITENV			0x47
-#define POST_AGESA_AMDS3LATERESTORE		0x48
+#define POSTCODE_PSP_LOAD_SMU				0x46
+#define POSTCODE_AGESA_AMDINITENV			0x47
+#define POSTCODE_AGESA_AMDS3LATERESTORE			0x48
 
-#define POST_AGESA_AMDINITRESUME		0x60
-#define POST_AGESA_AMDINITRESUME_DONE		0x61
+#define POSTCODE_AGESA_AMDINITRESUME			0x60
+#define POSTCODE_AGESA_AMDINITRESUME_DONE		0x61
 
-#define POST_BOOTBLOCK_SOC_EARLY_INIT		0x90
+#define POSTCODE_BOOTBLOCK_SOC_EARLY_INIT		0x90
 
 
-#define POST_BOOTBLOCK_RESUME_ENTRY		0xb0
-#define POST_BOOTBLOCK_PRE_C_ENTRY		0xa0
-#define POST_BOOTBLOCK_PRE_C_DONE		0xa2
+#define POSTCODE_BOOTBLOCK_RESUME_ENTRY			0xb0
+#define POSTCODE_BOOTBLOCK_PRE_C_ENTRY			0xa0
+#define POSTCODE_BOOTBLOCK_PRE_C_DONE			0xa2
 
 #endif
diff --git a/src/soc/amd/common/psp_verstage/include/psp_post_code.h b/src/soc/amd/common/psp_verstage/include/psp_post_code.h
index 44464b6aa07b..56b2a80c409a 100644
--- a/src/soc/amd/common/psp_verstage/include/psp_post_code.h
+++ b/src/soc/amd/common/psp_verstage/include/psp_post_code.h
@@ -3,33 +3,33 @@
 #ifndef PSP_POST_CODE_H
 #define PSP_POST_CODE_H
 
-#define POSTCODE_ENTERED_PSP_VERSTAGE		0x00
-#define POSTCODE_CONSOLE_INIT			0x01
-#define POSTCODE_EARLY_INIT			0x02
-#define POSTCODE_LATE_INIT			0x03
-#define POSTCODE_VERSTAGE_MAIN			0x04
-#define POSTCODE_VERSTAGE_S0I3_RESUME		0x05
+#define POSTCODE_ENTERED_PSP_VERSTAGE			0x00
+#define POSTCODE_CONSOLE_INIT				0x01
+#define POSTCODE_EARLY_INIT				0x02
+#define POSTCODE_LATE_INIT				0x03
+#define POSTCODE_VERSTAGE_MAIN				0x04
+#define POSTCODE_VERSTAGE_S0I3_RESUME			0x05
 
-#define POSTCODE_SAVE_BUFFERS			0x0E
-#define POSTCODE_UPDATE_BOOT_REGION		0x0F
+#define POSTCODE_SAVE_BUFFERS				0x0E
+#define POSTCODE_UPDATE_BOOT_REGION			0x0F
 
-#define POSTCODE_DEFAULT_BUFFER_SIZE_NOTICE	0xC0
-#define POSTCODE_WORKBUF_RESIZE_WARNING		0xC1
-#define POSTCODE_WORKBUF_SAVE_ERROR		0xC2
-#define POSTCODE_WORKBUF_BUFFER_SIZE_ERROR	0xC3
-#define POSTCODE_ROMSIG_MISMATCH_ERROR		0xC4
-#define POSTCODE_PSP_COOKIE_MISMATCH_ERROR	0xC5
-#define POSTCODE_BHD_COOKIE_MISMATCH_ERROR	0xC6
-#define POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR	0xC7
-#define POSTCODE_FMAP_REGION_MISSING		0xC8
-#define POSTCODE_AMD_FW_MISSING			0xC9
-#define POSTCODE_CMOS_RECOVERY			0xCA
-#define POSTCODE_EARLY_INIT_ERROR		0xCB
-#define POSTCODE_INIT_TPM_FAILED		0xCC
-#define POSTCODE_MAP_SPI_ROM_FAILED		0xCD
+#define POSTCODE_DEFAULT_BUFFER_SIZE_NOTICE		0xC0
+#define POSTCODE_WORKBUF_RESIZE_WARNING			0xC1
+#define POSTCODE_WORKBUF_SAVE_ERROR			0xC2
+#define POSTCODE_WORKBUF_BUFFER_SIZE_ERROR		0xC3
+#define POSTCODE_ROMSIG_MISMATCH_ERROR			0xC4
+#define POSTCODE_PSP_COOKIE_MISMATCH_ERROR		0xC5
+#define POSTCODE_BHD_COOKIE_MISMATCH_ERROR		0xC6
+#define POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR		0xC7
+#define POSTCODE_FMAP_REGION_MISSING			0xC8
+#define POSTCODE_AMD_FW_MISSING				0xC9
+#define POSTCODE_CMOS_RECOVERY				0xCA
+#define POSTCODE_EARLY_INIT_ERROR			0xCB
+#define POSTCODE_INIT_TPM_FAILED			0xCC
+#define POSTCODE_MAP_SPI_ROM_FAILED			0xCD
 
-#define POSTCODE_UNMAP_SPI_ROM			0xF0
-#define POSTCODE_UNMAP_FCH_DEVICES		0xF1
-#define POSTCODE_LEAVING_VERSTAGE		0xF2
+#define POSTCODE_UNMAP_SPI_ROM				0xF0
+#define POSTCODE_UNMAP_FCH_DEVICES			0xF1
+#define POSTCODE_LEAVING_VERSTAGE			0xF2
 
 #endif
diff --git a/src/soc/amd/glinda/romstage.c b/src/soc/amd/glinda/romstage.c
index 2bf5e230c905..63a6b07dc632 100644
--- a/src/soc/amd/glinda/romstage.c
+++ b/src/soc/amd/glinda/romstage.c
@@ -13,7 +13,7 @@
 
 void __noreturn romstage_main(void)
 {
-	post_code(POST_ROMSTAGE_MAIN);
+	post_code(POSTCODE_ROMSTAGE_MAIN);
 
 	/* Snapshot chipset state prior to any FSP call */
 	fill_chipset_state();
diff --git a/src/soc/amd/mendocino/romstage.c b/src/soc/amd/mendocino/romstage.c
index 046c351f774b..83a8bf97504b 100644
--- a/src/soc/amd/mendocino/romstage.c
+++ b/src/soc/amd/mendocino/romstage.c
@@ -14,7 +14,7 @@
 
 void __noreturn romstage_main(void)
 {
-	post_code(POST_ROMSTAGE_MAIN);
+	post_code(POSTCODE_ROMSTAGE_MAIN);
 
 	if (CONFIG(WRITE_STB_BUFFER_TO_CONSOLE))
 		write_stb_to_console();
diff --git a/src/soc/amd/phoenix/romstage.c b/src/soc/amd/phoenix/romstage.c
index 2bf5e230c905..63a6b07dc632 100644
--- a/src/soc/amd/phoenix/romstage.c
+++ b/src/soc/amd/phoenix/romstage.c
@@ -13,7 +13,7 @@
 
 void __noreturn romstage_main(void)
 {
-	post_code(POST_ROMSTAGE_MAIN);
+	post_code(POSTCODE_ROMSTAGE_MAIN);
 
 	/* Snapshot chipset state prior to any FSP call */
 	fill_chipset_state();
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 846460df3baa..c43b249487be 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -14,7 +14,7 @@
 
 void __noreturn romstage_main(void)
 {
-	post_code(POST_ROMSTAGE_MAIN);
+	post_code(POSTCODE_ROMSTAGE_MAIN);
 
 	/* Snapshot chipset state prior to any FSP call. */
 	fill_chipset_state();
diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c
index 1d41477e4dcb..a1ddb5ce6d30 100644
--- a/src/soc/amd/stoneyridge/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock.c
@@ -77,7 +77,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 void bootblock_soc_early_init(void)
 {
 	bootblock_fch_early_init();
-	post_code(POST_BOOTBLOCK_SOC_EARLY_INIT);
+	post_code(POSTCODE_BOOTBLOCK_SOC_EARLY_INIT);
 }
 
 void bootblock_soc_init(void)
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c
index 60bc921d9383..eaa0e9ad6cb9 100644
--- a/src/soc/amd/stoneyridge/chip.c
+++ b/src/soc/amd/stoneyridge/chip.c
@@ -108,15 +108,15 @@ struct chip_operations soc_amd_stoneyridge_ops = {
 static void earliest_ramstage(void *unused)
 {
 	if (!acpi_is_wakeup_s3()) {
-		post_code(POST_PSP_LOAD_SMU);
+		post_code(POSTCODE_PSP_LOAD_SMU);
 		if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
 			psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2");
 
-		post_code(POST_AGESA_AMDINITENV);
+		post_code(POSTCODE_AGESA_AMDINITENV);
 		do_agesawrapper(AMD_INIT_ENV, "amdinitenv");
 	} else {
 		/* Complete the initial system restoration */
-		post_code(POST_AGESA_AMDS3LATERESTORE);
+		post_code(POSTCODE_AGESA_AMDS3LATERESTORE);
 		do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore");
 	}
 }
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 460218e73c56..fc918f916f34 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -37,10 +37,10 @@ void __weak mainboard_romstage_entry(void)
 
 static void agesa_call(void)
 {
-	post_code(POST_AGESA_AMDINITRESET);
+	post_code(POSTCODE_AGESA_AMDINITRESET);
 	do_agesawrapper(AMD_INIT_RESET, "amdinitreset");
 
-	post_code(POST_AGESA_AMDINITEARLY);
+	post_code(POSTCODE_AGESA_AMDINITEARLY);
 	/* APs will not exit amdinitearly */
 	do_agesawrapper(AMD_INIT_EARLY, "amdinitearly");
 }
@@ -68,10 +68,10 @@ void __noreturn romstage_main(void)
 	bsp_agesa_call();
 
 	if (!s3_resume) {
-		post_code(POST_AGESA_AMDINITPOST);
+		post_code(POSTCODE_AGESA_AMDINITPOST);
 		do_agesawrapper(AMD_INIT_POST, "amdinitpost");
 
-		post_code(POST_AGESA_AMDINITPOST_DONE);
+		post_code(POSTCODE_AGESA_AMDINITPOST_DONE);
 		/*
 		 * TODO: This is a hack to work around current AGESA behavior.
 		 *       AGESA needs to change to reflect that coreboot owns
@@ -101,16 +101,16 @@ void __noreturn romstage_main(void)
 		wrmsr(SYSCFG_MSR, sys_cfg);
 	} else {
 		printk(BIOS_INFO, "S3 detected\n");
-		post_code(POST_AGESA_AMDINITRESUME);
+		post_code(POSTCODE_AGESA_AMDINITRESUME);
 		do_agesawrapper(AMD_INIT_RESUME, "amdinitresume");
 
-		post_code(POST_AGESA_AMDINITRESUME_DONE);
+		post_code(POSTCODE_AGESA_AMDINITRESUME_DONE);
 	}
 
-	post_code(POST_PSP_NOTIFY_DRAM);
+	post_code(POSTCODE_PSP_NOTIFY_DRAM);
 	psp_notify_dram();
 
-	post_code(POST_PSP_NOTIFY_DRAM_DONE);
+	post_code(POSTCODE_PSP_NOTIFY_DRAM_DONE);
 	if (cbmem_recovery(s3_resume))
 		printk(BIOS_CRIT, "Failed to recover cbmem\n");
 	if (romstage_handoff_init(s3_resume))
@@ -119,7 +119,7 @@ void __noreturn romstage_main(void)
 	if (CONFIG(SMM_TSEG))
 		smm_list_regions();
 
-	post_code(POST_ROMSTAGE_RUN_POSTCAR);
+	post_code(POSTCODE_ROMSTAGE_RUN_POSTCAR);
 	prepare_and_run_postcar();
 }
 
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 5f6b6de07cda..3c8dc2e6869b 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -78,7 +78,7 @@
 .global bootblock_pre_c_entry
 bootblock_pre_c_entry:
 
-	post_code(POST_BOOTBLOCK_PRE_C_ENTRY)
+	post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY)
 
 /* Bootguard sets up its own CAR and needs separate handling */
 check_boot_guard:
@@ -98,7 +98,7 @@ no_bootguard:
 	jmp	check_mtrr /* Check if CPU properly reset */
 
 no_reset:
-	post_code(POST_SOC_NO_RESET)
+	post_code(POSTCODE_SOC_NO_RESET)
 
 	/* Clear/disable fixed MTRRs */
 	mov	$fixed_mtrr_list, %ebx
@@ -112,7 +112,7 @@ clear_fixed_mtrr:
 	cmp	$fixed_mtrr_list_end, %ebx
 	jl	clear_fixed_mtrr
 
-	post_code(POST_SOC_CLEAR_FIXED_MTRRS)
+	post_code(POSTCODE_SOC_CLEAR_FIXED_MTRRS)
 
 	/* Figure out how many MTRRs we have, and clear them out */
 	mov	$MTRR_CAP_MSR, %ecx
@@ -130,7 +130,7 @@ clear_var_mtrr:
 	dec	%ebx
 	jnz	clear_var_mtrr
 
-	post_code(POST_SOC_CLEAR_VAR_MTRRS)
+	post_code(POSTCODE_SOC_CLEAR_VAR_MTRRS)
 
 	/* Configure default memory type to uncacheable (UC) */
 	mov	$MTRR_DEF_TYPE_MSR, %ecx
@@ -158,7 +158,7 @@ setup_car_mtrr:
 	bts	%eax, %esi
 	dec	%esi			/* esi <- MTRR_PHYS_MASK_HIGH */
 
-	post_code(POST_SOC_SET_UP_CAR_MTRRS)
+	post_code(POSTCODE_SOC_SET_UP_CAR_MTRRS)
 
 #if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0)
 	find_free_mtrr
@@ -217,7 +217,7 @@ setup_car_mtrr:
 #else
 #error "DCACHE_RAM_SIZE is not a power of 2 and setup code is missing"
 #endif
-	post_code(POST_SOC_BOOTGUARD_SETUP)
+	post_code(POSTCODE_SOC_BOOTGUARD_SETUP)
 
 	is_bootguard_nem
 	jz	no_bootguard_car_continue
@@ -269,7 +269,7 @@ no_bootguard_car_continue:
 .global car_init_done
 car_init_done:
 
-	post_code(POST_SOC_CAR_INIT_DONE)
+	post_code(POSTCODE_SOC_CAR_INIT_DONE)
 
 	/* Setup bootblock stack */
 	mov	$_ecar_stack, %esp
@@ -296,7 +296,7 @@ car_init_done:
 #endif
 
 before_carstage:
-	post_code(POST_SOC_BEFORE_CARSTAGE)
+	post_code(POSTCODE_SOC_BEFORE_CARSTAGE)
 
 	call	bootblock_c_entry
 	/* Never reached */
@@ -329,11 +329,11 @@ car_nem:
 	or	$0x1, %eax
 	wrmsr
 
-	post_code(POST_SOC_CLEARING_CAR)
+	post_code(POSTCODE_SOC_CLEARING_CAR)
 
 	clear_car
 
-	post_code(POST_SOC_DISABLE_CACHE_EVICT)
+	post_code(POSTCODE_SOC_DISABLE_CACHE_EVICT)
 
 	/* Disable cache eviction (run stage) */
 	mov	$MSR_EVICT_CTL, %ecx
@@ -418,11 +418,11 @@ car_cqos:
 	and	%ebx, %eax
 	wrmsr
 
-	post_code(POST_SOC_CLEARING_CAR)
+	post_code(POSTCODE_SOC_CLEARING_CAR)
 
 	clear_car
 
-	post_code(POST_SOC_DISABLE_CACHE_EVICT)
+	post_code(POSTCODE_SOC_DISABLE_CACHE_EVICT)
 
 	/* Cache is populated. Use mask 1 that will block evicts */
 	mov	$IA32_PQR_ASSOC, %ecx
@@ -447,7 +447,7 @@ car_nem_enhanced:
 	rdmsr
 	or	$0x1, %eax
 	wrmsr
-	post_code(POST_SOC_CAR_NEM_ENHANCED)
+	post_code(POSTCODE_SOC_CAR_NEM_ENHANCED)
 
 	/* Create n-way set associativity of cache */
 	xorl	%edi, %edi
@@ -634,7 +634,7 @@ program_sf2:
 #endif
 	wrmsr
 
-	post_code(POST_SOC_DISABLE_CACHE_EVICT)
+	post_code(POSTCODE_SOC_DISABLE_CACHE_EVICT)
 	/*
 	 * Enable No-Eviction Mode Run State by setting
 	 * NO_EVICT_MODE MSR 2E0h bit [1] = '1'.
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 14637cedc4d7..939c793d1a05 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -610,7 +610,7 @@ int heci_reset(void)
 	uint32_t csr;
 
 	/* Clear post code to prevent eventlog entry from unknown code. */
-	post_code(POST_CODE_ZERO);
+	post_code(POSTCODE_CODE_ZERO);
 
 	/* Send reset request */
 	csr = read_host_csr();
diff --git a/src/soc/intel/common/block/include/intelblocks/post_codes.h b/src/soc/intel/common/block/include/intelblocks/post_codes.h
index 7c78ef8e0e0a..c4cd2ab04d65 100644
--- a/src/soc/intel/common/block/include/intelblocks/post_codes.h
+++ b/src/soc/intel/common/block/include/intelblocks/post_codes.h
@@ -4,18 +4,18 @@
 #define SOC_INTEL_COMMON_BLOCK_POST_CODES_H
 
 /* common/block/cpu/car/cache_as_ram.s */
-#define POST_BOOTBLOCK_PRE_C_ENTRY			0x20
-#define POST_SOC_NO_RESET				0x21
-#define POST_SOC_CLEAR_FIXED_MTRRS			0x22
-#define POST_SOC_CLEAR_VAR_MTRRS			0x23
-#define POST_SOC_SET_UP_CAR_MTRRS			0x24
-#define POST_SOC_BOOTGUARD_SETUP			0x25
-#define POST_SOC_CLEARING_CAR				0x26
-#define POST_SOC_DISABLE_CACHE_EVICT			0x27
-#define POST_SOC_CAR_NEM_ENHANCED			0x28
-#define POST_SOC_CAR_INIT_DONE				0x29
-#define POST_SOC_BEFORE_CARSTAGE			0x2a
+#define POSTCODE_BOOTBLOCK_PRE_C_ENTRY			0x20
+#define POSTCODE_SOC_NO_RESET				0x21
+#define POSTCODE_SOC_CLEAR_FIXED_MTRRS			0x22
+#define POSTCODE_SOC_CLEAR_VAR_MTRRS			0x23
+#define POSTCODE_SOC_SET_UP_CAR_MTRRS			0x24
+#define POSTCODE_SOC_BOOTGUARD_SETUP			0x25
+#define POSTCODE_SOC_CLEARING_CAR			0x26
+#define POSTCODE_SOC_DISABLE_CACHE_EVICT		0x27
+#define POSTCODE_SOC_CAR_NEM_ENHANCED			0x28
+#define POSTCODE_SOC_CAR_INIT_DONE			0x29
+#define POSTCODE_SOC_BEFORE_CARSTAGE			0x2a
 
 /* common/block/cse/cse.c */
-#define POST_CODE_ZERO					0x00
+#define POSTCODE_CODE_ZERO				0x00
 #endif