mb/google/brya: Move ACPI MPTS method from DSDT to SSDT for Brya and Redrix

This change is to move MPTS (Mainboard Prepare To Sleep) method from
wwan_power.asl to SSDT.

MPTS is mainboard-specific method, while wwan_power.asl is meant for
WWAN from its name.

Having fixed MPTS method (i.e. DSDT) can not cover the case where device
only presents and certain CBI bit(s) is(are) set.

In Redrix and Brya, there are SKUs with or without 5G, 4G device. For
those with 4G, MPTS method should be different. For those with no WWAN
device, no MPTS is needed.

Having MPTS generating in SSDT also eliminates the need for introducing
Kconfig flags to support different devices in the future.
MPTS method is created inside mainboard_fill_ssdt function in which the
corresponding variant function is called.

This will generate the following for the mainboard:
Scope (\_SB)
{
    Method (MPTS, 1, Serialized)
    {
        Local0 = \_SB.PCI0.RP01.RTD3._STA ()
        If ((Local0 == One))
        {
            \_SB.PCI0.RP01.PXSX.DPTS (Arg0)
        }
    }
}

Test:
Check the SSDT for MPTS method under \_SB after boot to OS
Use shutdown command and check the GPIO pins from logical analyzer

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I0f0b7638e90a7862173fca99305398bb250373e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

7 files changed, 55 insertions, 12 deletions

diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 7235b03285b5..f88f4292bdf5 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -36,8 +36,6 @@ config BOARD_GOOGLE_BRYA0
 	select BOARD_GOOGLE_BASEBOARD_BRYA
 	select DRIVERS_GENESYSLOGIC_GL9755
 	select DRIVERS_INTEL_MIPI_CAMERA
-	select HAVE_PCIE_WWAN
-	select HAVE_WWAN_POWER_SEQUENCE
 	select SOC_INTEL_COMMON_BLOCK_IPU
 	select SOC_INTEL_CRASHLOG
 
@@ -46,8 +44,6 @@ config BOARD_GOOGLE_BRYA4ES
 	select BOARD_GOOGLE_BASEBOARD_BRYA
 	select DRIVERS_GENESYSLOGIC_GL9755
 	select DRIVERS_INTEL_MIPI_CAMERA
-	select HAVE_PCIE_WWAN
-	select HAVE_WWAN_POWER_SEQUENCE
 	select SOC_INTEL_COMMON_BLOCK_IPU
 	select SOC_INTEL_CRASHLOG
 
@@ -118,8 +114,6 @@ config BOARD_GOOGLE_REDRIX
 	select DRIVERS_I2C_MAX98390
 	select DRIVERS_INTEL_MIPI_CAMERA
 	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
-	select HAVE_PCIE_WWAN
-	select HAVE_WWAN_POWER_SEQUENCE
 	select SOC_INTEL_COMMON_BLOCK_IPU
 
 config BOARD_GOOGLE_REDRIX4ES
@@ -132,8 +126,6 @@ config BOARD_GOOGLE_REDRIX4ES
 	select DRIVERS_I2C_MAX98390
 	select DRIVERS_INTEL_MIPI_CAMERA
 	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
-	select HAVE_PCIE_WWAN
-	select HAVE_WWAN_POWER_SEQUENCE
 	select SOC_INTEL_COMMON_BLOCK_IPU
 
 config BOARD_GOOGLE_TAEKO
diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c
index 536eabc8581c..488eb889ccf4 100644
--- a/src/mainboard/google/brya/mainboard.c
+++ b/src/mainboard/google/brya/mainboard.c
@@ -5,6 +5,10 @@
 #include <ec/ec.h>
 #include <soc/ramstage.h>
 #include <fw_config.h>
+#include <acpi/acpigen.h>
+#include <drivers/wwan/fm/chip.h>
+
+WEAK_DEV_PTR(rp6_wwan);
 
 static void add_fw_config_oem_string(const struct fw_config *config, void *arg)
 {
@@ -55,10 +59,54 @@ static void mainboard_dev_init(struct device *dev)
 	mainboard_ec_init();
 }
 
+static void mainboard_generate_shutdown(const struct device *dev)
+{
+	const struct drivers_wwan_fm_config *config = config_of(dev);
+	const struct device *parent = dev->bus->dev;
+
+	if (!config)
+		return;
+	if (config->rtd3dev) {
+		acpigen_write_store();
+		acpigen_emit_namestring(acpi_device_path_join(parent, "RTD3._STA"));
+		acpigen_emit_byte(LOCAL0_OP);
+		acpigen_write_if_lequal_op_int(LOCAL0_OP, ONE_OP);
+		{
+			acpigen_emit_namestring(acpi_device_path_join(dev, "DPTS"));
+			acpigen_emit_byte(ARG0_OP);
+		}
+		acpigen_write_if_end();
+	} else {
+		acpigen_emit_namestring(acpi_device_path_join(dev, "DPTS"));
+		acpigen_emit_byte(ARG0_OP);
+	}
+}
+
+static void mainboard_fill_ssdt(const struct device *dev)
+{
+	const struct device *wwan = DEV_PTR(rp6_wwan);
+
+	if (wwan) {
+		acpigen_write_scope("\\_SB");
+		acpigen_write_method_serialized("MPTS", 1);
+		mainboard_generate_shutdown(wwan);
+		acpigen_write_method_end(); /* Method */
+		acpigen_write_scope_end(); /* Scope */
+	}
+	/* for variant to fill additional SSDT */
+	variant_fill_ssdt(dev);
+}
+
+void __weak variant_fill_ssdt(const struct device *dev)
+{
+	/* Add board-specific SSDT entries */
+}
+
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_dev_init;
 	dev->ops->get_smbios_strings = mainboard_smbios_strings;
+	dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
index b3a10e0a6467..7c1ce21f6cbe 100644
--- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
@@ -23,6 +23,7 @@ void variant_get_spd_info(struct mem_spd *spd_info);
 int variant_memory_sku(void);
 bool variant_is_half_populated(void);
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config);
+void variant_fill_ssdt(const struct device *dev);
 
 /* Modify devictree settings during ramstage */
 void variant_devtree_update(void);
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index 9f3e0285a6b0..d18e9df19ec9 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -198,7 +198,7 @@ chip soc/intel/alderlake
 				register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
 				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
 				use rp6_rtd3 as rtd3dev
-				device generic 0 on
+				device generic 0 alias rp6_wwan on
 					probe DB_LTE LTE_PCIE
 				end
 			end
diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb
index 13d028ea69b6..ac968ba686b8 100644
--- a/src/mainboard/google/brya/variants/brya4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb
@@ -195,7 +195,7 @@ chip soc/intel/alderlake
 				register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
 				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
 				use rp6_rtd3 as rtd3dev
-				device generic 0 on
+				device generic 0 alias rp6_wwan on
 					probe DB_LTE LTE_PCIE
 				end
 			end
diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb
index 62a24eda6890..2bf3fc23be3f 100644
--- a/src/mainboard/google/brya/variants/redrix/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb
@@ -92,6 +92,7 @@ chip soc/intel/alderlake
 		},
 	}"
 	register "tcc_offset" = "3"  # TCC of 97C
+
 	device domain 0 on
 		device ref igpu on
 			chip drivers/gfx/generic
@@ -178,7 +179,7 @@ chip soc/intel/alderlake
 				register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
 				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
 				use rp6_rtd3 as rtd3dev
-				device generic 0 on
+				device generic 0 alias rp6_wwan on
 					probe DB_LTE LTE_PCIE
 				end
 			end
diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
index 5cb105df657f..afffab533356 100644
--- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
@@ -78,6 +78,7 @@ chip soc/intel/alderlake
 		},
 	}"
 	register "tcc_offset" = "3"  # TCC of 97C
+
 	device domain 0 on
 		device ref igpu on
 			chip drivers/gfx/generic
@@ -164,7 +165,7 @@ chip soc/intel/alderlake
 				register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
 				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
 				use rp6_rtd3 as rtd3dev
-				device generic 0 on
+				device generic 0 alias rp6_wwan on
 					probe DB_LTE LTE_PCIE
 				end
 			end