soc/qualcomm/x1p42100: Add QUP Serial Engine (SE) entries

This patch adds QUP-SE entries as applicable for the Qualcomm X1P-42-100
SoC.

This includes:
- Add new entries for QUPV3_2 SEs.
- Update base addresses for all QUP-SEs.
- Base GPIO pin function assignments.
- Definition and GPIO mapping for relevant QUP Serial Engines (SEs).
- GPIO mapping for the QSPI interface.

Additionally, update GPIO PINS for QSPI and UART.

BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.

Change-Id: Ib0535aa5dfadef8c412c5e9dd51859068539821f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>

6 files changed, 435 insertions, 29 deletions

diff --git a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
index 5bb39e3bb517..a119d172957a 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/addressmap.h
@@ -5,35 +5,34 @@
 
 #include <stdint.h>
 
-/* TODO: update as per datasheet */
 #define AOSS_CC_BASE			0x0C2A0000
 #define QSPI_BASE			0x088DC000
 #define TLMM_TILE_BASE			0x0F100000
 
 /* X1P42100 QSPI GPIO PINS */
-#define QSPI_CS				GPIO(0)
-#define QSPI_DATA_0			GPIO(0)
-#define QSPI_DATA_1			GPIO(0)
-#define QSPI_CLK			GPIO(0)
+#define QSPI_CS				GPIO(132)
+#define QSPI_DATA_0			GPIO(128)
+#define QSPI_DATA_1			GPIO(129)
+#define QSPI_CLK			GPIO(127)
 
-#define GPIO_FUNC_QSPI_DATA_0		0
-#define GPIO_FUNC_QSPI_DATA_1		0
-#define GPIO_FUNC_QSPI_CLK		0
+#define GPIO_FUNC_QSPI_DATA_0		GPIO128_FUNC_QSPI0_DATA_0
+#define GPIO_FUNC_QSPI_DATA_1		GPIO129_FUNC_QSPI0_DATA_1
+#define GPIO_FUNC_QSPI_CLK		GPIO127_FUNC_QSPI0_CLK
 
 /*
  * QUP SERIAL ENGINE BASE ADDRESSES
  */
 /* QUPV3_0 */
-#define QUP_SERIAL0_BASE		0x00980000
-#define QUP_SERIAL1_BASE		0x00984000
-#define QUP_SERIAL2_BASE		0x00988000
-#define QUP_SERIAL3_BASE		0x0098C000
-#define QUP_SERIAL4_BASE		0x00990000
-#define QUP_SERIAL5_BASE		0x00994000
-#define QUP_SERIAL6_BASE		0x00998000
-#define QUP_SERIAL7_BASE		0x0099C000
-#define QUP_WRAP0_BASE			0x009C0000
-#define QUP_0_GSI_BASE			0x00904000
+#define QUP_SERIAL0_BASE		0x00B80000
+#define QUP_SERIAL1_BASE		0x00B84000
+#define QUP_SERIAL2_BASE		0x00B88000
+#define QUP_SERIAL3_BASE		0x00B8C000
+#define QUP_SERIAL4_BASE		0x00B90000
+#define QUP_SERIAL5_BASE		0x00B94000
+#define QUP_SERIAL6_BASE		0x00B98000
+#define QUP_SERIAL7_BASE		0x00B9C000
+#define QUP_WRAP0_BASE			0x00BC0000
+#define QUP_0_GSI_BASE			0x00B04000
 
 /* QUPV3_1 */
 #define QUP_SERIAL8_BASE		0x00A80000
@@ -47,7 +46,16 @@
 #define QUP_WRAP1_BASE			0x00AC0000
 #define QUP_1_GSI_BASE			0x00A04000
 
-/* QUPV3_2 - Dummy Entry */
-#define QUP_WRAP2_BASE			0x00000000
+/* QUPV3_2 */
+#define QUP_SERIAL16_BASE		0x00880000
+#define QUP_SERIAL17_BASE		0x00884000
+#define QUP_SERIAL18_BASE		0x00888000
+#define QUP_SERIAL19_BASE		0x0088C000
+#define QUP_SERIAL20_BASE		0x00890000
+#define QUP_SERIAL21_BASE		0x00894000
+#define QUP_SERIAL22_BASE		0x00898000
+#define QUP_SERIAL23_BASE		0x0089C000
+#define QUP_WRAP2_BASE			0x008C0000
+#define QUP_2_GSI_BASE			0x00804000
 
 #endif /*  __SOC_QUALCOMM_X1P42100_ADDRESS_MAP_H__ */
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index 97d418fdbbd9..c6b01f8f91f9 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -9,6 +9,33 @@
 
 #define SRC_XO_HZ		(38400 * KHz)
 
+enum clk_qup {
+	QUP_WRAP0_S0,
+	QUP_WRAP0_S1,
+	QUP_WRAP0_S2,
+	QUP_WRAP0_S3,
+	QUP_WRAP0_S4,
+	QUP_WRAP0_S5,
+	QUP_WRAP0_S6,
+	QUP_WRAP0_S7,
+	QUP_WRAP1_S0,
+	QUP_WRAP1_S1,
+	QUP_WRAP1_S2,
+	QUP_WRAP1_S3,
+	QUP_WRAP1_S4,
+	QUP_WRAP1_S5,
+	QUP_WRAP1_S6,
+	QUP_WRAP1_S7,
+	QUP_WRAP2_S0,
+	QUP_WRAP2_S1,
+	QUP_WRAP2_S2,
+	QUP_WRAP2_S3,
+	QUP_WRAP2_S4,
+	QUP_WRAP2_S5,
+	QUP_WRAP2_S6,
+	QUP_WRAP2_S7,
+};
+
 /* TODO: update as per datasheet */
 void clock_configure_qspi(uint32_t hz);
 void clock_enable_qup(int qup);
diff --git a/src/soc/qualcomm/x1p42100/include/soc/gpio.h b/src/soc/qualcomm/x1p42100/include/soc/gpio.h
index 1c30f7881f59..d9eaab83a1b9 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/gpio.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/gpio.h
@@ -7,16 +7,255 @@
 #include <soc/addressmap.h>
 #include <soc/gpio_common.h>
 
-#define PIN(index, func1, func2, func3, func4) \
+#define PIN(index, func1, func2, func3, func4, func5, func6) \
 GPIO##index##_ADDR = TLMM_TILE_BASE + (index * TLMM_GPIO_OFF_DELTA), \
 GPIO##index##_FUNC_##func1 = 1, \
 GPIO##index##_FUNC_##func2 = 2, \
 GPIO##index##_FUNC_##func3 = 3, \
-GPIO##index##_FUNC_##func4 = 4
+GPIO##index##_FUNC_##func4 = 4, \
+GPIO##index##_FUNC_##func5 = 5, \
+GPIO##index##_FUNC_##func6 = 6
 
-/* TODO: update as per datasheet */
 enum {
-	PIN(0, QUP0_L0, RES_2, RES_3, RES_4),
+	PIN(0, QUP0_SE0_L0, IBI_I3C_QUP0_SE0_SDA, RES_3, RES_4, RES_5, RES_6),
+	PIN(1, QUP0_SE0_L1, IBI_I3C_QUP0_SE0_SCL, RES_3, RES_4, RES_5, RES_6),
+	PIN(2, QUP0_SE0_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(3, QUP0_SE0_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(4, QUP0_SE1_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(5, QUP0_SE1_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(6, QUP0_SE1_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(7, QUP0_SE1_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(8, QUP0_SE2_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(9, QUP0_SE2_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(10, QUP0_SE2_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(11, QUP0_SE2_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(12, QUP0_SE3_L0, QUP0_SE7_L2, RES_3, RES_4, RES_5, RES_6),
+	PIN(13, QUP0_SE3_L1, QUP0_SE7_L3, RES_3, RES_4, RES_5, RES_6),
+	PIN(14, QUP0_SE3_L2, QUP0_SE7_L0, RES_3, RES_4, RES_5, RES_6),
+	PIN(15, QUP0_SE3_L3, QUP0_SE7_L1, RES_3, RES_4, RES_5, RES_6),
+	PIN(16, QUP0_SE4_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(17, QUP0_SE4_L1, QUP0_SE2_L4, RES_3, RES_4, RES_5, RES_6),
+	PIN(18, QUP0_SE4_L2, QUP0_SE2_L5, RES_3, RES_4, QDSS_CTI_TRIG0_OUT_MIRB, RES_6),
+	PIN(19, QUP0_SE4_L3, QUP0_SE2_L6, RES_3, RES_4, QDSS_CTI_TRIG1_OUT_MIRB, RES_6),
+	PIN(20, QUP0_SE5_L0, GP_PDM_MIRB_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(21, QUP0_SE5_L1, QUP0_SE3_L6, GP_PDM_MIRB_1, RES_4, RES_5, RES_6),
+	PIN(22, QUP0_SE5_L2, QUP0_SE3_L5, GP_PDM_MIRB_0, RES_4, RES_5, RES_6),
+	PIN(23, QUP0_SE5_L3, QUP0_SE3_L4, RES_3, RES_4, QDSS_CTI_TRIG0_IN_MIRA, RES_6),
+	PIN(24, QUP0_SE6_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(25, QUP0_SE6_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(26, QUP0_SE6_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(27, QUP0_SE6_L3, RES_2, RES_3, QDSS_CTI_TRIG1_IN_MIRA, RES_5, RES_6),
+	PIN(28, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(29, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(30, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(31, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(32, QUP1_SE0_L0, IBI_I3C_QUP1_SE0_SDA, RES_3, RES_4, RES_5, RES_6),
+	PIN(33, QUP1_SE0_L1, IBI_I3C_QUP1_SE0_SCL, QUP1_SE3_L6, RES_4, RES_5, RES_6),
+	PIN(34, QUP1_SE0_L2, QUP1_SE3_L5, TSENSE_PWM1_OUT_MIRNAT, TSENSE_PWM2_OUT_MIRNAT,
+		 TSENSE_PWM3_OUT_MIRNAT, TSENSE_PWM4_OUT_MIRNAT),
+	PIN(35, QUP1_SE0_L3, QUP1_SE3_L4, PLL_CLK_AUX, RES_4, RES_5, RES_6),
+	PIN(36, QUP1_SE1_L0, IBI_I3C_QUP1_SE1_SDA, RES_3, RES_4, RES_5, RES_6),
+	PIN(37, QUP1_SE1_L1, IBI_I3C_QUP1_SE1_SCL, RES_3, RES_4, RES_5, RES_6),
+	PIN(38, QUP1_SE1_L2, VSENSE_TRIGGER_MIRNAT, RES_3, RES_4, RES_5, RES_6),
+	PIN(39, QUP1_SE1_L3, SYS_THROTTLE_MIRA, RES_3, RES_4, RES_5, RES_6),
+	PIN(40, QUP1_SE2_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(41, QUP1_SE2_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(42, QUP1_SE2_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(43, QUP1_SE2_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(44, QUP1_SE3_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(45, QUP1_SE3_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(46, QUP1_SE3_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(47, QUP1_SE3_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(48, QUP1_SE4_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(49, QUP1_SE4_L1, QUP1_SE2_L4, RES_3, RES_4, RES_5, RES_6),
+	PIN(50, QUP1_SE4_L2, QUP1_SE2_L5, RES_3, RES_4, RES_5, RES_6),
+	PIN(51, QUP1_SE4_L3, QUP1_SE2_L6, RES_3, RES_4, RES_5, RES_6),
+	PIN(52, QUP1_SE5_L0, QUP1_SE7_L2, RES_3, RES_4, RES_5, RES_6),
+	PIN(53, QUP1_SE5_L1, QUP1_SE7_L3, GP_MN, RES_4, RES_5, RES_6),
+	PIN(54, QUP1_SE5_L2, QUP1_SE7_L0, RES_3, RES_4, RES_5, RES_6),
+	PIN(55, QUP1_SE5_L3, QUP1_SE7_L1, RES_3, RES_4, RES_5, RES_6),
+	PIN(56, QUP1_SE6_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(57, QUP1_SE6_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(58, QUP1_SE6_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(59, QUP1_SE6_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(60, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(61, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(62, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(63, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(64, QUP2_SE0_L0, GCC_GP2_CLK_MIRB, RES_3, RES_4, RES_5, RES_6),
+	PIN(65, QUP2_SE0_L1, QUP2_SE3_L6, TGU_CH1_TRIGOUT, RES_4, RES_5, RES_6),
+	PIN(66, QUP2_SE0_L2, QUP2_SE3_L5, TGU_CH2_TRIGOUT, RES_4, RES_5, RES_6),
+	PIN(67, QUP2_SE0_L3, QUP2_SE3_L4, TGU_CH3_TRIGOUT, RES_4, RES_5, RES_6),
+	PIN(68, QUP2_SE1_L0, IBI_I3C_QUP2_SE1_SDA, TGU_CH4_TRIGOUT, RES_4, RES_5, RES_6),
+	PIN(69, QUP2_SE1_L1, IBI_I3C_QUP2_SE1_SCL, TGU_CH5_TRIGOUT, RES_4, RES_5, RES_6),
+	PIN(70, QUP2_SE1_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(71, QUP2_SE1_L3, GCC_GP1_CLK_MIRB, RES_3, RES_4, RES_5, RES_6),
+	PIN(72, QUP2_SE2_L0, GCC_GP1_CLK_MIRA, RES_3, RES_4, RES_5, RES_6),
+	PIN(73, QUP2_SE2_L1, GCC_GP2_CLK_MIRA, RES_3, RES_4, RES_5, RES_6),
+	PIN(74, QUP2_SE2_L2, GCC_GP3_CLK_MIRA, RES_3, RES_4, RES_5, RES_6),
+	PIN(75, QUP2_SE2_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(76, QUP2_SE3_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(77, QUP2_SE3_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(78, QUP2_SE3_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(79, QUP2_SE3_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(80, QUP2_SE4_L0, TGU_CH7_TRIGOUT, RES_3, RES_4, RES_5, RES_6),
+	PIN(81, QUP2_SE4_L1, QUP2_SE2_L4, TGU_CH0_TRIGOUT, RES_4, RES_5, RES_6),
+	PIN(82, QUP2_SE4_L2, QUP2_SE2_L5, GCC_GP3_CLK_MIRB, RES_4, RES_5, RES_6),
+	PIN(83, QUP2_SE4_L3, QUP2_SE2_L6, TGU_CH6_TRIGOUT, RES_4, RES_5, RES_6),
+	PIN(84, QUP2_SE5_L0, QUP2_SE7_L2, RES_3, RES_4, RES_5, RES_6),
+	PIN(85, QUP2_SE5_L1, QUP2_SE7_L3, RES_3, RES_4, RES_5, RES_6),
+	PIN(86, QUP2_SE5_L2, QUP2_SE7_L0, RES_3, RES_4, RES_5, RES_6),
+	PIN(87, QUP2_SE5_L3, QUP2_SE7_L1, RES_3, RES_4, RES_5, RES_6),
+	PIN(88, QUP2_SE6_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(89, QUP2_SE6_L1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(90, QUP2_SE6_L2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(91, QUP2_SE6_L3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(92, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(93, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(94, SYS_THROTTLE_MIRB, RES_2, MDP_VSYNC_P, RES_4, RES_5, RES_6),
+	PIN(95, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(96, CAM_MCLK0, QDSS_GPIO_TRACEDATA_LOCA_0, RES_3, RES_4, RES_5, RES_6),
+	PIN(97, CAM_MCLK1, QDSS_GPIO_TRACEDATA_LOCA_1, RES_3, RES_4, RES_5, RES_6),
+	PIN(98, CAM_MCLK2, QDSS_GPIO_TRACEDATA_LOCA_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(99, RES_1, QDSS_GPIO_TRACEDATA_LOCA_3, RES_3, RES_4, RES_5, RES_6),
+	PIN(100, CAM_AON_MCLK4, QDSS_GPIO_TRACEDATA_LOCA_4, RES_3, RES_4, RES_5, RES_6),
+	PIN(101, CCI_I2C_SDA0, QDSS_GPIO_TRACEDATA_LOCA_5, RES_3, RES_4, RES_5, RES_6),
+	PIN(102, CCI_I2C_SCL0, QDSS_GPIO_TRACEDATA_LOCA_6, RES_3, RES_4, RES_5, RES_6),
+	PIN(103, CCI_I2C_SDA1, QDSS_GPIO_TRACEDATA_LOCA_7, RES_3, RES_4, RES_5, RES_6),
+	PIN(104, CCI_I2C_SCL1, QDSS_GPIO_TRACECTL_LOCA, RES_3, RES_4, RES_5, RES_6),
+	PIN(105, CCI_I2C_SDA2, QDSS_GPIO_TRACECLK_LOCA, RES_3, RES_4, RES_5, RES_6),
+	PIN(106, CCI_I2C_SCL2, QDSS_GPIO_TRACEDATA_LOCA_8, RES_3, RES_4, RES_5, RES_6),
+	PIN(107, QDSS_GPIO_TRACEDATA_LOCA_9, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(108, QDSS_GPIO_TRACEDATA_LOCA_10, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(109, CCI_TIMER0, MDP_VSYNC4_OUT, QDSS_GPIO_TRACEDATA_LOCA_11, RES_4, RES_5, RES_6),
+	PIN(110, CCI_TIMER1, MDP_VSYNC5_OUT, QDSS_GPIO_TRACEDATA_LOCA_12, RES_4, RES_5, RES_6),
+	PIN(111, CCI_TIMER2, CCI_ASYNC_IN2, MDP_VSYNC6_OUT, QDSS_GPIO_TRACEDATA_LOCA_13, RES_5, RES_6),
+	PIN(112, CCI_TIMER3, CCI_ASYNC_IN1, MDP_VSYNC7_OUT, QDSS_GPIO_TRACEDATA_LOCA_14, RES_5, RES_6),
+	PIN(113, CCI_TIMER4, CCI_ASYNC_IN0, MDP_VSYNC8_OUT, QDSS_GPIO_TRACEDATA_LOCA_15, RES_5, RES_6),
+	PIN(114, RES_2, MDP_VSYNC0_OUT, MDP_VSYNC1_OUT, RES_4, RES_5, RES_6),
+	PIN(115, RES_2, MDP_VSYNC3_OUT, MDP_VSYNC2_OUT, RES_4, RES_5, RES_6),
+	PIN(116, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(117, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(118, HOST2WLAN_SOL, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(119, EDP0_HOT_PLUG_DETECT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(120, EDP1_HOT_PLUG_DETECT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(121, USB0_PHY_PS, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(122, USB0_DP_HOT_PLUG_DETECT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(123, USB1_PHY_PS, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(124, USB1_DP_HOT_PLUG_DETECT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(125, USB2_PHY_PS, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(126, USB2_DP_HOT_PLUG_DETECT, GP_PDM_MIRA_0, RES_3, RES_4, RES_5, RES_6),
+	PIN(127, QSPI0_CLK, RES_2, GP_PDM_MIRA_1, RES_4, RES_5, RES_6),
+	PIN(128, QSPI0_DATA_0, RES_2, GP_PDM_MIRA_2, RES_4, RES_5, RES_6),
+	PIN(129, QSPI0_DATA_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(130, QSPI0_DATA_2, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(131, QSPI0_DATA_3, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(132, QSPI0_CS0_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(133, QSPI0_CS1_N, RES_2, TB_TRIG_SDC1, RES_4, RES_5, RES_6),
+	PIN(134, AUDIO_EXT_MCLK0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(135, I2S0_SCK, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(136, I2S0_DATA0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(137, I2S0_DATA1, TB_TRIG_SDC2, RES_3, RES_4, RES_5, RES_6),
+	PIN(138, I2S0_WS, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(139, I2S1_SCK, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(140, I2S1_DATA0, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(141, I2S1_WS, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(142, I2S1_DATA1, AUDIO_EXT_MCLK1, AUDIO_REF_CLK, RES_4, RES_5, RES_6),
+	PIN(143, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(144, PCIE3_CLK_REQ_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(145, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(146, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(147, PCIE4_CLK_REQ_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(148, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(149, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(150, PCIE5_CLK_REQ_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(151, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(152, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(153, PCIE6_CLK_REQ_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(154, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(155, MDP_VSYNC_S, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(156, RES_2, MDP_VSYNC_E, RES_3, RES_4, RES_5, RES_6),
+	PIN(157, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(158, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(159, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(160, RESOUT_GPIO_N, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(161, QDSS_CTI_TRIG0_OUT_MIRA, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(162, SD_WRITE_PROTECT, QDSS_CTI_TRIG1_OUT_MIRA, RES_3, RES_4, RES_5, RES_6),
+	PIN(163, USB0_SBRX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(164, USB0_SBTX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(165, USB0_SBTX_DIR_OUT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(166, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(167, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(168, EUSB0_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(169, EUSB3_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(170, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(171, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(172, USB1_SBRX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(173, USB1_SBTX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(174, USB1_SBTX_DIR_OUT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(175, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(176, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(177, EUSB1_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(178, EUSB6_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(179, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(180, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(181, USB2_SBRX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(182, USB2_SBTX, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(183, USB2_SBTX_DIR_OUT, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(184, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(185, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(186, EUSB2_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(187, EUSB5_AC_EN, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(188, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(189, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(190, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(191, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(192, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(193, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(194, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(195, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(196, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(197, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(198, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(199, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(200, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(201, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(202, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(203, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(204, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(205, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(206, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(207, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(208, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(209, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(210, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(211, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(212, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(213, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(214, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(215, RES_2, QDSS_CTI_TRIG1_IN_MIRB, RES_3, RES_4, RES_5, RES_6),
+	PIN(216, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(217, RES_2, QDSS_CTI_TRIG0_IN_MIRB, RES_3, RES_4, RES_5, RES_6),
+	PIN(218, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(219, RES_1, QDSS_GPIO_TRACEDATA_LOCB_0, RES_3, RES_4, RES_5, RES_6),
+	PIN(220, RES_1, QDSS_GPIO_TRACEDATA_LOCB_1, RES_3, RES_4, RES_5, RES_6),
+	PIN(221, RES_1, QDSS_GPIO_TRACEDATA_LOCB_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(222, RES_1, QDSS_GPIO_TRACEDATA_LOCB_3, RES_3, RES_4, RES_5, RES_6),
+	PIN(223, RES_1, QDSS_GPIO_TRACEDATA_LOCB_4, RES_3, RES_4, RES_5, RES_6),
+	PIN(224, RES_1, QDSS_GPIO_TRACEDATA_LOCB_5, RES_3, RES_4, RES_5, RES_6),
+	PIN(225, RES_1, QDSS_GPIO_TRACEDATA_LOCB_6, RES_3, RES_4, RES_5, RES_6),
+	PIN(226, RES_1, QDSS_GPIO_TRACEDATA_LOCB_7, RES_3, RES_4, RES_5, RES_6),
+	PIN(227, RES_1, QDSS_GPIO_TRACECLK_LOCB, RES_3, RES_4, RES_5, RES_6),
+	PIN(228, RES_1, QDSS_GPIO_TRACECTL_LOCB, RES_3, RES_4, RES_5, RES_6),
+	PIN(229, QDSS_GPIO_TRACEDATA_LOCB_8, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(230, QDSS_GPIO_TRACEDATA_LOCB_9, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(231, QDSS_GPIO_TRACEDATA_LOCB_10, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(232, QDSS_GPIO_TRACEDATA_LOCB_11, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(233, QDSS_GPIO_TRACEDATA_LOCB_12, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(234, QDSS_GPIO_TRACEDATA_LOCB_13, RES_2, RES_3, RES_4, RES_5, RES_6),
+	PIN(235, AON_CCI_I2C_SDA3, QDSS_GPIO_TRACEDATA_LOCB_14, RES_3, RES_4, RES_5, RES_6),
+	PIN(236, AON_CCI_I2C_SCL3, QDSS_GPIO_TRACEDATA_LOCB_15, RES_3, RES_4, RES_5, RES_6),
+	PIN(237, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6),
 };
 
 #endif /* _SOC_QUALCOMM_X1P42100_GPIO_H_ */
diff --git a/src/soc/qualcomm/x1p42100/include/soc/qcom_qup_se.h b/src/soc/qualcomm/x1p42100/include/soc/qcom_qup_se.h
index f12616a51fb0..a8f48c549ce6 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/qcom_qup_se.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/qcom_qup_se.h
@@ -10,7 +10,6 @@
 #include <timer.h>
 #include <types.h>
 
-/* TODO: update qup_se entries as per datasheet */
 enum qup_se {
 	QUPV3_0_SE0,
 	QUPV3_0_SE1,
@@ -20,7 +19,22 @@ enum qup_se {
 	QUPV3_0_SE5,
 	QUPV3_0_SE6,
 	QUPV3_0_SE7,
-	QUPV3_0_SE8,
+	QUPV3_1_SE0,
+	QUPV3_1_SE1,
+	QUPV3_1_SE2,
+	QUPV3_1_SE3,
+	QUPV3_1_SE4,
+	QUPV3_1_SE5,
+	QUPV3_1_SE6,
+	QUPV3_1_SE7,
+	QUPV3_2_SE0,
+	QUPV3_2_SE1,
+	QUPV3_2_SE2,
+	QUPV3_2_SE3,
+	QUPV3_2_SE4,
+	QUPV3_2_SE5,
+	QUPV3_2_SE6,
+	QUPV3_2_SE7,
 	QUPV3_SE_MAX,
 };
 
diff --git a/src/soc/qualcomm/x1p42100/include/soc/uart.h b/src/soc/qualcomm/x1p42100/include/soc/uart.h
index 179deb302126..4b0383194285 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/uart.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/uart.h
@@ -3,6 +3,6 @@
 #ifndef _SOC_QUALCOMM_X1P42100_UART_TX_H_
 #define _SOC_QUALCOMM_X1P42100_UART_TX_H_
 
-#define UART_TX_PIN GPIO(0)
+#define UART_TX_PIN GPIO(86)
 
 #endif /* _SOC_QUALCOMM_X1P42100_UART_TX_H_ */
diff --git a/src/soc/qualcomm/x1p42100/qcom_qup_se.c b/src/soc/qualcomm/x1p42100/qcom_qup_se.c
index 8b2284d4b1e5..a3217d4a630d 100644
--- a/src/soc/qualcomm/x1p42100/qcom_qup_se.c
+++ b/src/soc/qualcomm/x1p42100/qcom_qup_se.c
@@ -2,7 +2,125 @@
 
 #include <soc/qcom_qup_se.h>
 
-/* TODO: update qup entries as per datasheet */
 struct qup qup[QUPV3_SE_MAX] = {
-
+	[QUPV3_0_SE0] = { .regs = (void *)QUP_SERIAL0_BASE,
+		.pin = { GPIO(0), GPIO(1), GPIO(2), GPIO(3) },
+		.func = { GPIO0_FUNC_QUP0_SE0_L0, GPIO1_FUNC_QUP0_SE0_L1,
+			GPIO2_FUNC_QUP0_SE0_L2, GPIO3_FUNC_QUP0_SE0_L3 }
+		},
+	[QUPV3_0_SE1] = { .regs = (void *)QUP_SERIAL1_BASE,
+		.pin = { GPIO(4), GPIO(5), GPIO(6), GPIO(7) },
+		.func = { GPIO4_FUNC_QUP0_SE1_L0, GPIO5_FUNC_QUP0_SE1_L1,
+			GPIO6_FUNC_QUP0_SE1_L2, GPIO7_FUNC_QUP0_SE1_L3 }
+		},
+	[QUPV3_0_SE2] = { .regs = (void *)QUP_SERIAL2_BASE,
+		.pin = { GPIO(8), GPIO(9), GPIO(10), GPIO(11) },
+		.func = { GPIO8_FUNC_QUP0_SE2_L0, GPIO9_FUNC_QUP0_SE2_L1,
+			GPIO10_FUNC_QUP0_SE2_L2, GPIO11_FUNC_QUP0_SE2_L3 }
+		},
+	[QUPV3_0_SE3] = { .regs = (void *)QUP_SERIAL3_BASE,
+		.pin = { GPIO(12), GPIO(13), GPIO(14), GPIO(15) },
+		.func = { GPIO12_FUNC_QUP0_SE3_L0, GPIO13_FUNC_QUP0_SE3_L1,
+			GPIO14_FUNC_QUP0_SE3_L2, GPIO15_FUNC_QUP0_SE3_L3 }
+		},
+	[QUPV3_0_SE4] = { .regs = (void *)QUP_SERIAL4_BASE,
+		.pin = { GPIO(16), GPIO(17), GPIO(18), GPIO(19) },
+		.func = { GPIO16_FUNC_QUP0_SE4_L0, GPIO17_FUNC_QUP0_SE4_L1,
+			GPIO18_FUNC_QUP0_SE4_L2, GPIO19_FUNC_QUP0_SE4_L3 }
+		},
+	[QUPV3_0_SE5] = { .regs = (void *)QUP_SERIAL5_BASE,
+		.pin = { GPIO(20), GPIO(21), GPIO(22), GPIO(23) },
+		.func = { GPIO20_FUNC_QUP0_SE5_L0, GPIO21_FUNC_QUP0_SE5_L1,
+			GPIO22_FUNC_QUP0_SE5_L2, GPIO23_FUNC_QUP0_SE5_L3 }
+		},
+	[QUPV3_0_SE6] = { .regs = (void *)QUP_SERIAL6_BASE,
+		.pin = { GPIO(24), GPIO(25), GPIO(26), GPIO(27) },
+		.func = { GPIO24_FUNC_QUP0_SE6_L0, GPIO25_FUNC_QUP0_SE6_L1,
+			GPIO26_FUNC_QUP0_SE6_L2, GPIO27_FUNC_QUP0_SE6_L3 }
+		},
+	[QUPV3_0_SE7] = { .regs = (void *)QUP_SERIAL7_BASE,
+		.pin = { GPIO(14), GPIO(15), GPIO(12), GPIO(13) },
+		.func = { GPIO14_FUNC_QUP0_SE7_L0, GPIO15_FUNC_QUP0_SE7_L1,
+			GPIO12_FUNC_QUP0_SE7_L2, GPIO13_FUNC_QUP0_SE7_L3 }
+		},
+	[QUPV3_1_SE0] = { .regs = (void *)QUP_SERIAL8_BASE,
+		.pin = { GPIO(32), GPIO(33), GPIO(34), GPIO(35) },
+		.func = { GPIO32_FUNC_QUP1_SE0_L0, GPIO33_FUNC_QUP1_SE0_L1,
+			GPIO34_FUNC_QUP1_SE0_L2, GPIO35_FUNC_QUP1_SE0_L3 }
+		},
+	[QUPV3_1_SE1] = { .regs = (void *)QUP_SERIAL9_BASE,
+		.pin = { GPIO(36), GPIO(37), GPIO(38), GPIO(39) },
+		.func = { GPIO36_FUNC_QUP1_SE1_L0, GPIO37_FUNC_QUP1_SE1_L1,
+			GPIO38_FUNC_QUP1_SE1_L2, GPIO39_FUNC_QUP1_SE1_L3 }
+		},
+	[QUPV3_1_SE2] = { .regs = (void *)QUP_SERIAL10_BASE,
+		.pin = { GPIO(40), GPIO(41), GPIO(42), GPIO(43) },
+		.func = { GPIO40_FUNC_QUP1_SE2_L0, GPIO41_FUNC_QUP1_SE2_L1,
+			GPIO42_FUNC_QUP1_SE2_L2, GPIO43_FUNC_QUP1_SE2_L3 }
+		},
+	[QUPV3_1_SE3] = { .regs = (void *)QUP_SERIAL11_BASE,
+		.pin = { GPIO(44), GPIO(45), GPIO(46), GPIO(47) },
+		.func = { GPIO44_FUNC_QUP1_SE3_L0, GPIO45_FUNC_QUP1_SE3_L1,
+			GPIO46_FUNC_QUP1_SE3_L2, GPIO47_FUNC_QUP1_SE3_L3 }
+		},
+	[QUPV3_1_SE4] = { .regs = (void *)QUP_SERIAL12_BASE,
+		.pin = { GPIO(48), GPIO(49), GPIO(50), GPIO(51) },
+		.func = { GPIO48_FUNC_QUP1_SE4_L0, GPIO49_FUNC_QUP1_SE4_L1,
+			GPIO50_FUNC_QUP1_SE4_L2, GPIO51_FUNC_QUP1_SE4_L3 }
+		},
+	[QUPV3_1_SE5] = { .regs = (void *)QUP_SERIAL13_BASE,
+		.pin = { GPIO(52), GPIO(53), GPIO(54), GPIO(55) },
+		.func = { GPIO52_FUNC_QUP1_SE5_L0, GPIO53_FUNC_QUP1_SE5_L1,
+			GPIO54_FUNC_QUP1_SE5_L2, GPIO55_FUNC_QUP1_SE5_L3 }
+		},
+	[QUPV3_1_SE6] = { .regs = (void *)QUP_SERIAL14_BASE,
+		.pin = { GPIO(56), GPIO(57), GPIO(58), GPIO(59) },
+		.func = { GPIO56_FUNC_QUP1_SE6_L0, GPIO57_FUNC_QUP1_SE6_L1,
+			GPIO58_FUNC_QUP1_SE6_L2, GPIO59_FUNC_QUP1_SE6_L3 }
+		},
+	[QUPV3_1_SE7] = { .regs = (void *)QUP_SERIAL15_BASE,
+		.pin = { GPIO(54), GPIO(55), GPIO(52), GPIO(53) },
+		.func = { GPIO54_FUNC_QUP1_SE7_L0, GPIO55_FUNC_QUP1_SE7_L1,
+			GPIO52_FUNC_QUP1_SE7_L2, GPIO53_FUNC_QUP1_SE7_L3 }
+		},
+	[QUPV3_2_SE0] = { .regs = (void *)QUP_SERIAL16_BASE,
+		.pin = { GPIO(64), GPIO(65), GPIO(66), GPIO(67) },
+		.func = { GPIO64_FUNC_QUP2_SE0_L0, GPIO65_FUNC_QUP2_SE0_L1,
+			GPIO66_FUNC_QUP2_SE0_L2, GPIO67_FUNC_QUP2_SE0_L3 }
+		},
+	[QUPV3_2_SE1] = { .regs = (void *)QUP_SERIAL17_BASE,
+		.pin = { GPIO(68), GPIO(69), GPIO(70), GPIO(71) },
+		.func = { GPIO68_FUNC_QUP2_SE1_L0, GPIO69_FUNC_QUP2_SE1_L1,
+			GPIO70_FUNC_QUP2_SE1_L2, GPIO71_FUNC_QUP2_SE1_L3 }
+		},
+	[QUPV3_2_SE2] = { .regs = (void *)QUP_SERIAL18_BASE,
+		.pin = { GPIO(72), GPIO(73), GPIO(74), GPIO(75) },
+		.func = { GPIO72_FUNC_QUP2_SE2_L0, GPIO73_FUNC_QUP2_SE2_L1,
+			GPIO74_FUNC_QUP2_SE2_L2, GPIO75_FUNC_QUP2_SE2_L3 }
+		},
+	[QUPV3_2_SE3] = { .regs = (void *)QUP_SERIAL19_BASE,
+		.pin = { GPIO(76), GPIO(77), GPIO(78), GPIO(79) },
+		.func = { GPIO76_FUNC_QUP2_SE3_L0, GPIO77_FUNC_QUP2_SE3_L1,
+			GPIO78_FUNC_QUP2_SE3_L2, GPIO79_FUNC_QUP2_SE3_L3 }
+		},
+	[QUPV3_2_SE4] = { .regs = (void *)QUP_SERIAL20_BASE,
+		.pin = { GPIO(80), GPIO(81), GPIO(82), GPIO(83) },
+		.func = { GPIO80_FUNC_QUP2_SE4_L0, GPIO81_FUNC_QUP2_SE4_L1,
+			GPIO82_FUNC_QUP2_SE4_L2, GPIO83_FUNC_QUP2_SE4_L3 }
+		},
+	[QUPV3_2_SE5] = { .regs = (void *)QUP_SERIAL21_BASE,
+		.pin = { GPIO(84), GPIO(85), GPIO(86), GPIO(87) },
+		.func = { GPIO84_FUNC_QUP2_SE5_L0, GPIO85_FUNC_QUP2_SE5_L1,
+			GPIO86_FUNC_QUP2_SE5_L2, GPIO87_FUNC_QUP2_SE5_L3 }
+		},
+	[QUPV3_2_SE6] = { .regs = (void *)QUP_SERIAL22_BASE,
+		.pin = { GPIO(88), GPIO(89), GPIO(90), GPIO(91) },
+		.func = { GPIO88_FUNC_QUP2_SE6_L0, GPIO89_FUNC_QUP2_SE6_L1,
+			GPIO90_FUNC_QUP2_SE6_L2, GPIO91_FUNC_QUP2_SE6_L3 }
+		},
+	[QUPV3_2_SE7] = { .regs = (void *)QUP_SERIAL23_BASE,
+		.pin = { GPIO(86), GPIO(87), GPIO(84), GPIO(85) },
+		.func = { GPIO86_FUNC_QUP2_SE7_L0, GPIO87_FUNC_QUP2_SE7_L1,
+			GPIO84_FUNC_QUP2_SE7_L2, GPIO85_FUNC_QUP2_SE7_L3 }
+		},
 };