nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree

Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69294
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

11 files changed, 22 insertions, 12 deletions

diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
index bcce778cb11f..358fcf44b03a 100644
--- a/src/mainboard/apple/macbook21/devicetree.cb
+++ b/src/mainboard/apple/macbook21/devicetree.cb
@@ -14,6 +14,7 @@ chip northbridge/intel/i945
 	register "gpu_panel_power_cycle_delay" = "2"
 
 	device cpu_cluster 0 on
+		ops i945_cpu_bus_ops
 		chip cpu/intel/socket_m
 			device lapic 0 on end
 		end
@@ -22,6 +23,7 @@ chip northbridge/intel/i945
 	register "pci_mmio_size" = "768"
 
 	device domain 0 on
+		ops i945_pci_domain_ops
 		device pci 00.0 on # Host bridge
 			subsystemid 0x8086 0x7270
 		end
diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb
index 172f65f6536a..ad9b961dca00 100644
--- a/src/mainboard/asus/p5gc-mx/devicetree.cb
+++ b/src/mainboard/asus/p5gc-mx/devicetree.cb
@@ -3,6 +3,7 @@
 chip northbridge/intel/i945
 
 	device cpu_cluster 0 on
+		ops i945_cpu_bus_ops
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
@@ -12,6 +13,7 @@ chip northbridge/intel/i945
 	end
 
 	device domain 0 on
+		ops i945_pci_domain_ops
 		device pci 00.0 on # host bridge
 			subsystemid 0x1458 0x5000
 		end
diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb
index 9a91b81ee71a..345bbd81af18 100644
--- a/src/mainboard/getac/p470/devicetree.cb
+++ b/src/mainboard/getac/p470/devicetree.cb
@@ -6,6 +6,7 @@ chip northbridge/intel/i945
 	register "gfx.did" = "{ 0x80000100, 0x80000410, 0x80000320, 0x80000410, 0x00000005 }"
 
 	device cpu_cluster 0 on
+		ops i945_cpu_bus_ops
 		chip cpu/intel/socket_m
 			device lapic 0 on end
 		end
@@ -14,6 +15,7 @@ chip northbridge/intel/i945
 	register "pci_mmio_size" = "768"
 
 	device domain 0 on
+		ops i945_pci_domain_ops
 		device pci 00.0 on end # host bridge
 		device pci 01.0 off end # i945 PCIe root port
 		device pci 02.0 on end # vga controller
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
index c0f198f4e769..28af26fe97ce 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
@@ -3,6 +3,7 @@
 chip northbridge/intel/i945
 
 	device cpu_cluster 0 on
+		ops i945_cpu_bus_ops
 		chip cpu/intel/socket_LGA775
 			device lapic 0 on end
 		end
@@ -14,6 +15,7 @@ chip northbridge/intel/i945
 	register "pci_mmio_size" = "768"
 
 	device domain 0 on
+		ops i945_pci_domain_ops
 		device pci 00.0 on # host bridge
 			subsystemid 0x1458 0x5000
 		end
diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb
index 12104e4bb069..1b59fcc1b9da 100644
--- a/src/mainboard/ibase/mb899/devicetree.cb
+++ b/src/mainboard/ibase/mb899/devicetree.cb
@@ -3,6 +3,7 @@ chip northbridge/intel/i945
 	register "gfx" = "GMA_STATIC_DISPLAYS(0)"
 
 	device cpu_cluster 0 on
+		ops i945_cpu_bus_ops
 		chip cpu/intel/socket_m
 			device lapic 0 on end
 		end
@@ -11,6 +12,7 @@ chip northbridge/intel/i945
 	register "pci_mmio_size" = "768"
 
 	device domain 0 on
+		ops i945_pci_domain_ops
 		device pci 00.0 on end # host bridge
 		device pci 01.0 off end # i945 PCIe root port
 		device pci 02.0 on end # vga controller
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
index 669122fb5c8e..0238e04a485e 100644
--- a/src/mainboard/intel/d945gclf/devicetree.cb
+++ b/src/mainboard/intel/d945gclf/devicetree.cb
@@ -3,6 +3,7 @@
 chip northbridge/intel/i945
 
 	device cpu_cluster 0 on
+		ops i945_cpu_bus_ops
 		chip cpu/intel/socket_441
 			device lapic 0 on end
 		end
@@ -11,6 +12,7 @@ chip northbridge/intel/i945
 	register "pci_mmio_size" = "768"
 
 	device domain 0 on
+		ops i945_pci_domain_ops
 		subsystemid 0x8086 0x464c inherit
 		device pci 00.0 on  end # host bridge
 		device pci 01.0 off end # i945 PCIe root port
diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb
index bd0db6dd9215..90da56ceb93e 100644
--- a/src/mainboard/kontron/986lcd-m/devicetree.cb
+++ b/src/mainboard/kontron/986lcd-m/devicetree.cb
@@ -3,6 +3,7 @@ chip northbridge/intel/i945
 	register "gfx" = "GMA_STATIC_DISPLAYS(0)"
 
 	device cpu_cluster 0 on
+		ops i945_cpu_bus_ops
 		chip cpu/intel/socket_m
 			device lapic 0 on end
 		end
@@ -11,6 +12,7 @@ chip northbridge/intel/i945
 	register "pci_mmio_size" = "768"
 
 	device domain 0 on
+		ops i945_pci_domain_ops
 		device pci 00.0 on end # host bridge
 		device pci 01.0 off end # i945 PCIe x16 bridge
 		device pci 02.0 on end # GMA950 iGPU + VGA
diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
index 7709a8794985..c77af6bb2613 100644
--- a/src/mainboard/lenovo/t60/devicetree.cb
+++ b/src/mainboard/lenovo/t60/devicetree.cb
@@ -14,6 +14,7 @@ chip northbridge/intel/i945
 	register "gpu_panel_power_cycle_delay" = "2"
 
 	device cpu_cluster 0 on
+		ops i945_cpu_bus_ops
 		chip cpu/intel/socket_m
 			device lapic 0 on end
 		end
@@ -22,6 +23,7 @@ chip northbridge/intel/i945
 	register "pci_mmio_size" = "768"
 
 	device domain 0 on
+		ops i945_pci_domain_ops
 		device pci 00.0 on # Host bridge
 			subsystemid 0x17aa 0x2015
 		end
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index 862006292845..d56ec514aab9 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -14,6 +14,7 @@ chip northbridge/intel/i945
 	register "gpu_panel_power_cycle_delay" = "2"
 
 	device cpu_cluster 0 on
+		ops i945_cpu_bus_ops
 		chip cpu/intel/socket_m
 			device lapic 0 on end
 		end
@@ -22,6 +23,7 @@ chip northbridge/intel/i945
 	register "pci_mmio_size" = "768"
 
 	device domain 0 on
+		ops i945_pci_domain_ops
 		device pci 00.0 on # Host bridge
 			subsystemid 0x17aa 0x2017
 		end
diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb
index 6b9dbd912610..4023af809738 100644
--- a/src/mainboard/roda/rk886ex/devicetree.cb
+++ b/src/mainboard/roda/rk886ex/devicetree.cb
@@ -5,6 +5,7 @@ chip northbridge/intel/i945
 	register "gfx" = "GMA_STATIC_DISPLAYS(0)"
 
 	device cpu_cluster 0 on
+		ops i945_cpu_bus_ops
 		chip cpu/intel/socket_m
 			device lapic 0 on end
 		end
@@ -13,6 +14,7 @@ chip northbridge/intel/i945
 	register "pci_mmio_size" = "768"
 
 	device domain 0 on
+		ops i945_pci_domain_ops
 		subsystemid 0x4352 0x6886 inherit
 		device pci 00.0 on  end	# host bridge
 		# auto detection:
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 3c5603c90fc5..c175576d3a86 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -122,7 +122,7 @@ void northbridge_write_smram(u8 smram)
 	pci_write_config8(dev, SMRAM, smram);
 }
 
-static struct device_operations pci_domain_ops = {
+struct device_operations i945_pci_domain_ops = {
 	.read_resources   = mch_domain_read_resources,
 	.set_resources    = mch_domain_set_resources,
 	.scan_bus         = pci_domain_scan_bus,
@@ -155,22 +155,12 @@ static const struct pci_driver mc_driver __pci_driver = {
 	.devices = pci_device_ids,
 };
 
-static struct device_operations cpu_bus_ops = {
+struct device_operations i945_cpu_bus_ops = {
 	.read_resources   = noop_read_resources,
 	.set_resources    = noop_set_resources,
 	.init             = mp_cpu_bus_init,
 };
 
-static void enable_dev(struct device *dev)
-{
-	/* Set the operations if it is a special bus type */
-	if (dev->path.type == DEVICE_PATH_DOMAIN)
-		dev->ops = &pci_domain_ops;
-	else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
-		dev->ops = &cpu_bus_ops;
-}
-
 struct chip_operations northbridge_intel_i945_ops = {
 	CHIP_NAME("Intel i945 Northbridge")
-	.enable_dev = enable_dev,
 };