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| author | Stefan Reinauer <reinauer@chromium.org> | 2013-03-21 11:51:41 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-22 00:00:09 +0100 |
| commit | 24d1d4b47274eb82893e6726472a991a36fce0aa (patch) | |
| tree | 57126316330f6f9d407f605fa831ce530650f069 /src | |
| parent | 55ed3106556a9bcbe36d3389dc5230d4a4ee2a40 (diff) | |
| download | coreboot-24d1d4b47274eb82893e6726472a991a36fce0aa.tar.gz coreboot-24d1d4b47274eb82893e6726472a991a36fce0aa.tar.bz2 coreboot-24d1d4b47274eb82893e6726472a991a36fce0aa.zip | |
x86: Unify arch/io.h and arch/romcc_io.h
Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.
Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.
Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
410 files changed, 529 insertions, 876 deletions
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index ed8148e46531..a3555d81d3d6 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -141,7 +141,7 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_UNKNOWN 0xff #if !defined(__ROMCC__) -#if !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) && !defined(__SMM__) #include <device/device.h> int cpu_phys_address_size(void); @@ -162,7 +162,6 @@ struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); #else #include <arch/io.h> -#include <arch/romcc_io.h> #endif struct cpu_info { diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index f4c696767f87..29c83395a8e7 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -163,5 +163,348 @@ static inline __attribute__((always_inline)) void write32(unsigned long addr, ui *((volatile uint32_t *)(addr)) = value; } +#if defined(__PRE_RAM__) || defined(__SMM__) +static inline int log2(int value) +{ + unsigned int r = 0; + __asm__ volatile ( + "bsrl %1, %0\n\t" + "jnz 1f\n\t" + "movl $-1, %0\n\t" + "1:\n\t" + : "=r" (r) : "r" (value)); + return r; + +} +static inline int log2f(int value) +{ + unsigned int r = 0; + __asm__ volatile ( + "bsfl %1, %0\n\t" + "jnz 1f\n\t" + "movl $-1, %0\n\t" + "1:\n\t" + : "=r" (r) : "r" (value)); + return r; + +} + +#define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12) | \ + ((WHERE) & 0xFFF)) + +#define PCI_DEV(SEGBUS, DEV, FN) ( \ + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12)) + +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) + + +#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) + +typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */ + +/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, + * We don't need to set %fs, and %gs anymore + * Before that We need to use %gs, and leave %fs to other RAM access + */ + +static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0 +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + return inb(0xCFC + (addr & 3)); +} + +#if CONFIG_MMCONF_SUPPORT +static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where) +{ + unsigned addr; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; + return read8(addr); +} +#endif +static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where) +{ +#if CONFIG_MMCONF_SUPPORT_DEFAULT + return pci_mmio_read_config8(dev, where); +#else + return pci_io_read_config8(dev, where); +#endif +} + +static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + return inw(0xCFC + (addr & 2)); +} + +#if CONFIG_MMCONF_SUPPORT +static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where) +{ + unsigned addr; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1); + return read16(addr); +} +#endif + +static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where) +{ +#if CONFIG_MMCONF_SUPPORT_DEFAULT + return pci_mmio_read_config16(dev, where); +#else + return pci_io_read_config16(dev, where); +#endif +} + + +static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); +} + +#if CONFIG_MMCONF_SUPPORT +static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where) +{ + unsigned addr; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3); + return read32(addr); +} +#endif + +static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where) +{ +#if CONFIG_MMCONF_SUPPORT_DEFAULT + return pci_mmio_read_config32(dev, where); +#else + return pci_io_read_config32(dev, where); +#endif +} + +static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + outb(value, 0xCFC + (addr & 3)); +} + +#if CONFIG_MMCONF_SUPPORT +static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value) +{ + unsigned addr; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; + write8(addr, value); +} +#endif + +static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value) +{ +#if CONFIG_MMCONF_SUPPORT_DEFAULT + pci_mmio_write_config8(dev, where, value); +#else + pci_io_write_config8(dev, where, value); +#endif +} + + +static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + outw(value, 0xCFC + (addr & 2)); +} + +#if CONFIG_MMCONF_SUPPORT +static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value) +{ + unsigned addr; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1); + write16(addr, value); +} +#endif + +static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value) +{ +#if CONFIG_MMCONF_SUPPORT_DEFAULT + pci_mmio_write_config16(dev, where, value); +#else + pci_io_write_config16(dev, where, value); +#endif +} + + +static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); +} + +#if CONFIG_MMCONF_SUPPORT +static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value) +{ + unsigned addr; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3); + write32(addr, value); +} +#endif + +static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value) +{ +#if CONFIG_MMCONF_SUPPORT_DEFAULT + pci_mmio_write_config32(dev, where, value); +#else + pci_io_write_config32(dev, where, value); +#endif +} + +static inline __attribute__((always_inline)) void pci_or_config8(device_t dev, unsigned where, uint8_t value) +{ + pci_write_config8(dev, where, pci_read_config8(dev, where) | value); +} + +static inline __attribute__((always_inline)) void pci_or_config16(device_t dev, unsigned where, uint16_t value) +{ + pci_write_config16(dev, where, pci_read_config16(dev, where) | value); +} + +static inline __attribute__((always_inline)) void pci_or_config32(device_t dev, unsigned where, uint32_t value) +{ + pci_write_config32(dev, where, pci_read_config32(dev, where) | value); +} + +#define PCI_DEV_INVALID (0xffffffffU) +static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev) +{ + for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { + unsigned int id; + id = pci_io_read_config32(dev, 0); + if (id == pci_id) { + return dev; + } + } + return PCI_DEV_INVALID; +} + +static inline device_t pci_locate_device(unsigned pci_id, device_t dev) +{ + for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) { + return dev; + } + } + return PCI_DEV_INVALID; +} + +static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +{ + device_t dev, last; + + dev = PCI_DEV(bus, 0, 0); + last = PCI_DEV(bus, 31, 7); + + for(; dev <=last; dev += PCI_DEV(0,0,1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) { + return dev; + } + } + return PCI_DEV_INVALID; +} + +/* Generic functions for pnp devices */ +static inline __attribute__((always_inline)) void pnp_write_config(device_t dev, uint8_t reg, uint8_t value) +{ + unsigned port = dev >> 8; + outb(reg, port ); + outb(value, port +1); +} + +static inline __attribute__((always_inline)) uint8_t pnp_read_config(device_t dev, uint8_t reg) +{ + unsigned port = dev >> 8; + outb(reg, port); + return inb(port +1); +} + +static inline __attribute__((always_inline)) void pnp_set_logical_device(device_t dev) +{ + unsigned device = dev & 0xff; + pnp_write_config(dev, 0x07, device); +} + +static inline __attribute__((always_inline)) void pnp_set_enable(device_t dev, int enable) +{ + pnp_write_config(dev, 0x30, enable?0x1:0x0); +} + +static inline __attribute__((always_inline)) int pnp_read_enable(device_t dev) +{ + return !!pnp_read_config(dev, 0x30); +} + +static inline __attribute__((always_inline)) void pnp_set_iobase(device_t dev, unsigned index, unsigned iobase) +{ + pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); + pnp_write_config(dev, index + 1, iobase & 0xff); +} + +static inline __attribute__((always_inline)) uint16_t pnp_read_iobase(device_t dev, unsigned index) +{ + return ((uint16_t)(pnp_read_config(dev, index)) << 8) | pnp_read_config(dev, index + 1); +} + +static inline __attribute__((always_inline)) void pnp_set_irq(device_t dev, unsigned index, unsigned irq) +{ + pnp_write_config(dev, index, irq); +} + +static inline __attribute__((always_inline)) void pnp_set_drq(device_t dev, unsigned index, unsigned drq) +{ + pnp_write_config(dev, index, drq & 0xff); +} + +#endif /* __PRE_RAM__ */ + #endif diff --git a/src/arch/x86/include/arch/romcc_io.h b/src/arch/x86/include/arch/romcc_io.h deleted file mode 100644 index 0f949f52ef13..000000000000 --- a/src/arch/x86/include/arch/romcc_io.h +++ /dev/null @@ -1,350 +0,0 @@ -#ifndef ARCH_ROMCC_IO_H -#define ARCH_ROMCC_IO_H 1 - -#include <stdint.h> - -// arch/io.h is pulled in in many places but it could -// also be pulled in here for all romcc/romstage code. -// #include <arch/io.h> - -static inline int log2(int value) -{ - unsigned int r = 0; - __asm__ volatile ( - "bsrl %1, %0\n\t" - "jnz 1f\n\t" - "movl $-1, %0\n\t" - "1:\n\t" - : "=r" (r) : "r" (value)); - return r; - -} -static inline int log2f(int value) -{ - unsigned int r = 0; - __asm__ volatile ( - "bsfl %1, %0\n\t" - "jnz 1f\n\t" - "movl $-1, %0\n\t" - "1:\n\t" - : "=r" (r) : "r" (value)); - return r; - -} - -#define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12) | \ - ((WHERE) & 0xFFF)) - -#define PCI_DEV(SEGBUS, DEV, FN) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12)) - -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) - - -#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) - -typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */ - -/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, - * We don't need to set %fs, and %gs anymore - * Before that We need to use %gs, and leave %fs to other RAM access - */ - -static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0 -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - return inb(0xCFC + (addr & 3)); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; - return read8(addr); -} -#endif -static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - return pci_mmio_read_config8(dev, where); -#else - return pci_io_read_config8(dev, where); -#endif -} - -static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - return inw(0xCFC + (addr & 2)); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1); - return read16(addr); -} -#endif - -static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - return pci_mmio_read_config16(dev, where); -#else - return pci_io_read_config16(dev, where); -#endif -} - - -static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3); - return read32(addr); -} -#endif - -static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - return pci_mmio_read_config32(dev, where); -#else - return pci_io_read_config32(dev, where); -#endif -} - -static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; - write8(addr, value); -} -#endif - -static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - pci_mmio_write_config8(dev, where, value); -#else - pci_io_write_config8(dev, where, value); -#endif -} - - -static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outw(value, 0xCFC + (addr & 2)); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1); - write16(addr, value); -} -#endif - -static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - pci_mmio_write_config16(dev, where, value); -#else - pci_io_write_config16(dev, where, value); -#endif -} - - -static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3); - write32(addr, value); -} -#endif - -static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - pci_mmio_write_config32(dev, where, value); -#else - pci_io_write_config32(dev, where, value); -#endif -} - -static inline __attribute__((always_inline)) void pci_or_config8(device_t dev, unsigned where, uint8_t value) -{ - pci_write_config8(dev, where, pci_read_config8(dev, where) | value); -} - -static inline __attribute__((always_inline)) void pci_or_config16(device_t dev, unsigned where, uint16_t value) -{ - pci_write_config16(dev, where, pci_read_config16(dev, where) | value); -} - -static inline __attribute__((always_inline)) void pci_or_config32(device_t dev, unsigned where, uint32_t value) -{ - pci_write_config32(dev, where, pci_read_config32(dev, where) | value); -} - -#define PCI_DEV_INVALID (0xffffffffU) -static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev) -{ - for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { - unsigned int id; - id = pci_io_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return PCI_DEV_INVALID; -} - -static inline device_t pci_locate_device(unsigned pci_id, device_t dev) -{ - for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return PCI_DEV_INVALID; -} - -static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) -{ - device_t dev, last; - - dev = PCI_DEV(bus, 0, 0); - last = PCI_DEV(bus, 31, 7); - - for(; dev <=last; dev += PCI_DEV(0,0,1)) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return PCI_DEV_INVALID; -} - -/* Generic functions for pnp devices */ -static inline __attribute__((always_inline)) void pnp_write_config(device_t dev, uint8_t reg, uint8_t value) -{ - unsigned port = dev >> 8; - outb(reg, port ); - outb(value, port +1); -} - -static inline __attribute__((always_inline)) uint8_t pnp_read_config(device_t dev, uint8_t reg) -{ - unsigned port = dev >> 8; - outb(reg, port); - return inb(port +1); -} - -static inline __attribute__((always_inline)) void pnp_set_logical_device(device_t dev) -{ - unsigned device = dev & 0xff; - pnp_write_config(dev, 0x07, device); -} - -static inline __attribute__((always_inline)) void pnp_set_enable(device_t dev, int enable) -{ - pnp_write_config(dev, 0x30, enable?0x1:0x0); -} - -static inline __attribute__((always_inline)) int pnp_read_enable(device_t dev) -{ - return !!pnp_read_config(dev, 0x30); -} - -static inline __attribute__((always_inline)) void pnp_set_iobase(device_t dev, unsigned index, unsigned iobase) -{ - pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); - pnp_write_config(dev, index + 1, iobase & 0xff); -} - -static inline __attribute__((always_inline)) uint16_t pnp_read_iobase(device_t dev, unsigned index) -{ - return ((uint16_t)(pnp_read_config(dev, index)) << 8) | pnp_read_config(dev, index + 1); -} - -static inline __attribute__((always_inline)) void pnp_set_irq(device_t dev, unsigned index, unsigned irq) -{ - pnp_write_config(dev, index, irq); -} - -static inline __attribute__((always_inline)) void pnp_set_drq(device_t dev, unsigned index, unsigned drq) -{ - pnp_write_config(dev, index, drq & 0xff); -} - -#endif /* ARCH_ROMCC_IO_H */ diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index f9c3ba8d6f35..bb065c808d18 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -23,7 +23,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/intel/microcode/microcode.c> #include "haswell.h" diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 4ece6c2f9cdb..6164de54ed4e 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -30,7 +30,6 @@ #include <timestamp.h> #include <arch/io.h> #include <arch/stages.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> #include <cbmem.h> diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index a4f8fc387b7d..d3579f7471ed 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -23,7 +23,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/intel/microcode/microcode.c> #include "model_206ax.h" diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index b4b7f36dba3a..fc30909ae87b 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 1d2c86f6cad6..c13b4525d645 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <console/console.h> diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 67802d643112..116dafa19646 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index 3c330630e2de..98996197e7b6 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/x86/car.h> #include <delay.h> #include <uart8250.h> diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c index ad297fb93286..d3a6aaf6790c 100644 --- a/src/ec/acpi/ec.c +++ b/src/ec/acpi/ec.c @@ -138,6 +138,8 @@ void ec_set_ports(u16 cmd_reg, u16 data_reg) ec_data_reg = data_reg; } +#if !defined(__SMM__) && !defined(__PRE_RAM__) struct chip_operations ec_acpi_ops = { CHIP_NAME("ACPI Embedded Controller") }; +#endif diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index cd5471d4a4d4..5ae0178ebfee 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -21,12 +21,9 @@ #include <console/console.h> #include <arch/io.h> #include <delay.h> - -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pnp.h> +#ifndef __PRE_RAM__ #include <elog.h> #include <stdlib.h> #include <string.h> diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 1ef971244f37..137aa8108d02 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -22,10 +22,10 @@ #ifndef __PRE_RAM__ #include <console/console.h> +#include <arch/io.h> #include <device/device.h> #include <device/pnp.h> #include <stdlib.h> -#include <arch/io.h> #include <delay.h> #include <elog.h> #include "ec.h" diff --git a/src/ec/smsc/mec1308/ec.c b/src/ec/smsc/mec1308/ec.c index bfd3c14bca29..fdae5e4e56c3 100644 --- a/src/ec/smsc/mec1308/ec.c +++ b/src/ec/smsc/mec1308/ec.c @@ -119,6 +119,7 @@ void ec_set_ports(u16 cmd_reg, u16 data_reg) ec_data_reg = data_reg; } +#if !defined(__PRE_RAM__) && !defined(__SMM__) static void mec1308_enable(device_t dev) { struct ec_smsc_mec1308_config *conf = dev->chip_info; @@ -133,3 +134,4 @@ struct chip_operations ec_smsc_mec1308_ops = { CHIP_NAME("SMSC MEC1308 EC Mailbox Interface") .enable_dev = mec1308_enable }; +#endif diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index cf2d38997d8e..bed77de01740 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -3,7 +3,7 @@ #include <arch/cpu.h> -#if !defined(__ROMCC__) +#if !defined(__PRE_RAM__) && !defined(__SMM__) void cpu_initialize(unsigned int cpu_index); struct bus; void initialize_cpus(struct bus *cpu_bus); @@ -20,6 +20,6 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1); extern struct cpu_driver cpu_drivers[]; /** end of compile time generated pci driver array */ extern struct cpu_driver ecpu_drivers[]; -#endif /* !__ROMCC__ */ +#endif /* !__PRE_RAM__ && !__SMM__ */ #endif /* CPU_CPU_H */ diff --git a/src/include/device/device.h b/src/include/device/device.h index b248aafb7a17..521931020236 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -1,6 +1,7 @@ #ifndef DEVICE_H #define DEVICE_H +#ifndef __SMM__ #include <stdint.h> #include <stddef.h> #include <device/resource.h> @@ -222,4 +223,7 @@ ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus, ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); #endif +#else /* __SMM__ */ +#include <arch/io.h> +#endif /* __SMM__ */ #endif /* DEVICE_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 132c48c9d3ba..1f47dafeca7c 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -20,7 +20,7 @@ #include <device/pci_def.h> #include <device/resource.h> #include <device/device.h> -#ifndef __PRE_RAM__ +#if !defined(__PRE_RAM__) && !defined(__SMM__) #include <device/pci_ops.h> #include <device/pci_rom.h> diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 2efbf9da4950..20fbb9921ff4 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -1,6 +1,7 @@ #ifndef PCI_OPS_H #define PCI_OPS_H +#ifndef __SMM__ #include <stdint.h> #include <device/device.h> #include <arch/pci_ops.h> @@ -20,5 +21,6 @@ void pci_mmio_write_config8(device_t dev, unsigned int where, u8 val); void pci_mmio_write_config16(device_t dev, unsigned int where, u16 val); void pci_mmio_write_config32(device_t dev, unsigned int where, u32 val); #endif +#endif #endif /* PCI_OPS_H */ diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index 7eb2ac5a0973..f97b05dad081 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pnp_def.h> +#if !defined(__PRE_RAM__) && !defined(__SMM__) /* Primitive PNP resource manipulation */ void pnp_write_config(device_t dev, u8 reg, u8 value); u8 pnp_read_config(device_t dev, u8 reg); @@ -50,4 +51,5 @@ struct resource *pnp_get_resource(device_t dev, unsigned index); void pnp_enable_devices(struct device *dev, struct device_operations *ops, unsigned int functions, struct pnp_info *info); +#endif #endif /* DEVICE_PNP_H */ diff --git a/src/include/lib.h b/src/include/lib.h index 9d8108532c6d..40c76f2db0d7 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -24,7 +24,7 @@ #include <stdint.h> #ifndef __ROMCC__ /* romcc doesn't support prototypes. */ -#ifndef __PRE_RAM__ /* Conflicts with romcc_io.h */ +#ifndef __PRE_RAM__ /* Conflicts with inline function in arch/io.h */ /* Defined in src/lib/clog2.c */ unsigned long log2(unsigned long x); #endif diff --git a/src/lib/ne2k.c b/src/lib/ne2k.c index 09925f698cba..31470fca0866 100644 --- a/src/lib/ne2k.c +++ b/src/lib/ne2k.c @@ -38,7 +38,6 @@ SMC8416 PIO support added by Andrew Bettison (andrewb@zip.com.au) on 4/3/02 #include <ip_checksum.h> #include <console/ne2k.h> #include <arch/io.h> -//#include <arch/romcc_io.h> #define MEM_SIZE MEM_32768 #define TX_START 64 @@ -343,8 +342,6 @@ void ne2k_transmit(unsigned int eth_nic_base) { #ifdef __PRE_RAM__ -#include <arch/romcc_io.h> - static void ns8390_reset(unsigned int eth_nic_base) { int i; diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index e8880dea9242..63d34b213de7 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index dfa5ce0dc072..9e4b35b5aa65 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 385ab7e2785e..74f8404ab764 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/advansus/a785e-i/reset.c b/src/mainboard/advansus/a785e-i/reset.c index 3ce182ed43fc..678bc3d2672d 100644 --- a/src/mainboard/advansus/a785e-i/reset.c +++ b/src/mainboard/advansus/a785e-i/reset.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <reset.h> +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <arch/io.h> -#include <arch/romcc_io.h> +#include <reset.h> #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 9657ec3e7aa2..ae283a4a3df6 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -32,7 +32,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/advantech/pcm-5820/romstage.c b/src/mainboard/advantech/pcm-5820/romstage.c index da47816c3362..b710aada53ce 100644 --- a/src/mainboard/advantech/pcm-5820/romstage.c +++ b/src/mainboard/advantech/pcm-5820/romstage.c @@ -21,7 +21,6 @@ #include <stdint.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index aeb1bfb3d513..f7812165967c 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 50906815e106..44528a028ca3 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/amd/dinar/reset.c b/src/mainboard/amd/dinar/reset.c index d7ee5323de53..f2a2bcdadc1d 100644 --- a/src/mainboard/amd/dinar/reset.c +++ b/src/mainboard/amd/dinar/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index e1e04d80dc99..a59d142ba256 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> diff --git a/src/mainboard/amd/inagua/reset.c b/src/mainboard/amd/inagua/reset.c index 5958e772ddc6..bb2482b57b42 100644 --- a/src/mainboard/amd/inagua/reset.c +++ b/src/mainboard/amd/inagua/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index d1693c5952aa..a03d5a772ee3 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -25,7 +25,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 75fda78a86d6..2963ada3c9b8 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 98c91b47017d..d1c75ad339db 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 6076bc8af125..25f14e88ea8d 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/amd/persimmon/reset.c b/src/mainboard/amd/persimmon/reset.c index 5958e772ddc6..bb2482b57b42 100644 --- a/src/mainboard/amd/persimmon/reset.c +++ b/src/mainboard/amd/persimmon/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 2ed4a77d25f8..0c8c45614054 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 2ace3d0e99dc..2735cdad2fa0 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c index 710eae8d03b1..fa680fe3cc4b 100644 --- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c @@ -5,7 +5,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include "console/console.c" diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index db8cdb0bae50..8d985b7d57c2 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -8,7 +8,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 478b26db2e40..b77371901180 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/amd/south_station/reset.c b/src/mainboard/amd/south_station/reset.c index 5958e772ddc6..bb2482b57b42 100644 --- a/src/mainboard/amd/south_station/reset.c +++ b/src/mainboard/amd/south_station/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 09b0900db2c9..88c64904a6ec 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -25,7 +25,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 096dd7da5574..1f3e86dc965c 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 1437329ed7e9..a567c1be8427 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/amd/torpedo/reset.c b/src/mainboard/amd/torpedo/reset.c index 5958e772ddc6..bb2482b57b42 100644 --- a/src/mainboard/amd/torpedo/reset.c +++ b/src/mainboard/amd/torpedo/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 0c454e863bf4..8edba8022a4a 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> diff --git a/src/mainboard/amd/union_station/reset.c b/src/mainboard/amd/union_station/reset.c index 5958e772ddc6..bb2482b57b42 100644 --- a/src/mainboard/amd/union_station/reset.c +++ b/src/mainboard/amd/union_station/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 02aea1b56e32..4538157fdb02 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -25,7 +25,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index c80551e50e6e..9b9679219fda 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index 84dc7a322cf6..4df84163b712 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 8eec1faa36f9..135daecbf8e3 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/asi/mb_5blgp/romstage.c b/src/mainboard/asi/mb_5blgp/romstage.c index 327856b3cd47..d6613875eac1 100644 --- a/src/mainboard/asi/mb_5blgp/romstage.c +++ b/src/mainboard/asi/mb_5blgp/romstage.c @@ -21,7 +21,6 @@ #include <stdint.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" diff --git a/src/mainboard/asi/mb_5blmp/romstage.c b/src/mainboard/asi/mb_5blmp/romstage.c index abb137d86983..e8befe4ba12d 100644 --- a/src/mainboard/asi/mb_5blmp/romstage.c +++ b/src/mainboard/asi/mb_5blmp/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 46b6ab0305f6..74a5412caffd 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -28,7 +28,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/asrock/e350m1/reset.c b/src/mainboard/asrock/e350m1/reset.c index 5958e772ddc6..bb2482b57b42 100644 --- a/src/mainboard/asrock/e350m1/reset.c +++ b/src/mainboard/asrock/e350m1/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 3a1e7aa0d27d..79f963b52904 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index a9ab9441eabe..2d041b2a496c 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -29,7 +29,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 7441715ccb45..2219ff93bf6a 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -29,7 +29,6 @@ unsigned int get_sbdn(unsigned bus); #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index bb70a2157ac5..f4df3320fc5b 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -29,7 +29,6 @@ unsigned int get_sbdn(unsigned bus); #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c index 5251025793fe..cb63f45d2bab 100644 --- a/src/mainboard/asus/dsbf/romstage.c +++ b/src/mainboard/asus/dsbf/romstage.c @@ -23,7 +23,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 0cfdec897bdb..ca6f4ca2d8bd 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -29,7 +29,6 @@ unsigned int get_sbdn(unsigned bus); #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index bf8117804f83..e534d48150b3 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -30,7 +30,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 9e1ba92a4be3..dc60a6e1c46e 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -33,7 +33,6 @@ unsigned int get_sbdn(unsigned bus); #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index db6cfe452fa0..509df9057a24 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -33,7 +33,6 @@ unsigned int get_sbdn(unsigned bus); #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 633cb50bccd5..3e8dad818cf1 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index f1b631441e7d..a42b5ddcabe3 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/asus/m5a88-v/reset.c b/src/mainboard/asus/m5a88-v/reset.c index 3ce182ed43fc..678bc3d2672d 100644 --- a/src/mainboard/asus/m5a88-v/reset.c +++ b/src/mainboard/asus/m5a88-v/reset.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <reset.h> +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <arch/io.h> -#include <arch/romcc_io.h> +#include <reset.h> #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 87dbdb8a83f6..dbae2d35f19f 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -32,7 +32,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index a51e92bfcdeb..213120d60a59 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 221c8c41722b..20c4b3f461d6 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index 88be10c7a4a6..93849c22714a 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index 0e4bfa9ae7af..f6daa5e3f6c5 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index e8880dea9242..63d34b213de7 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 7e8ba579cb64..37629486b560 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/avalue/eax-785e/reset.c b/src/mainboard/avalue/eax-785e/reset.c index 3ce182ed43fc..678bc3d2672d 100644 --- a/src/mainboard/avalue/eax-785e/reset.c +++ b/src/mainboard/avalue/eax-785e/reset.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <reset.h> +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <arch/io.h> -#include <arch/romcc_io.h> +#include <reset.h> #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 902c730e4c1d..d4704e8029be 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -32,7 +32,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/axus/tc320/romstage.c b/src/mainboard/axus/tc320/romstage.c index e887a293cdfb..053da1775383 100644 --- a/src/mainboard/axus/tc320/romstage.c +++ b/src/mainboard/axus/tc320/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index f38644072100..c138d00f30d7 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/bcom/winnet100/romstage.c b/src/mainboard/bcom/winnet100/romstage.c index e887a293cdfb..053da1775383 100644 --- a/src/mainboard/bcom/winnet100/romstage.c +++ b/src/mainboard/bcom/winnet100/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index fa8f548011f9..a57f9f7c08e3 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/via/cn700/raminit.h" diff --git a/src/mainboard/bifferos/bifferboard/romstage.c b/src/mainboard/bifferos/bifferboard/romstage.c index e2be9b336797..cdf2544ba2e9 100644 --- a/src/mainboard/bifferos/bifferboard/romstage.c +++ b/src/mainboard/bifferos/bifferboard/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c index ac3ea6cd9cfb..029e21b60c05 100644 --- a/src/mainboard/biostar/m6tba/romstage.c +++ b/src/mainboard/biostar/m6tba/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 4bf421c7f728..f57e1418fb52 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index 9d75f16b0460..37b28df0ccfb 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index e5c791716478..7eefedda4ece 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <lib.h> diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c index a293842dc448..9f3da08b9626 100644 --- a/src/mainboard/digitallogic/msm586seg/romstage.c +++ b/src/mainboard/digitallogic/msm586seg/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index caafd2f3cd31..da16c99f8d30 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "cpu/x86/bist.h" diff --git a/src/mainboard/eaglelion/5bcm/romstage.c b/src/mainboard/eaglelion/5bcm/romstage.c index f1ee25de4f8c..2f803aa98d21 100644 --- a/src/mainboard/eaglelion/5bcm/romstage.c +++ b/src/mainboard/eaglelion/5bcm/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/emulation/qemu-x86/romstage.c b/src/mainboard/emulation/qemu-x86/romstage.c index e5107db1e9cd..3faf947e001c 100644 --- a/src/mainboard/emulation/qemu-x86/romstage.c +++ b/src/mainboard/emulation/qemu-x86/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 90fc25f582e5..90d38ebcc6e2 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -22,7 +22,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c index 4a5a3ffbbb8b..6122c82e9a1a 100644 --- a/src/mainboard/getac/p470/smihandler.c +++ b/src/mainboard/getac/p470/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/i82801gx.h" diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index 8fe0de6d87c6..89761c93ce1d 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index 2f5cb89788b3..85a899a4a3e5 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c index f4be1a54b267..9def81d7ac1e 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c @@ -28,7 +28,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 838f60277ae9..07ef567c520b 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/gigabyte/m57sli/ap_romstage.c b/src/mainboard/gigabyte/m57sli/ap_romstage.c index d6a5778e5583..df00eed17e39 100644 --- a/src/mainboard/gigabyte/m57sli/ap_romstage.c +++ b/src/mainboard/gigabyte/m57sli/ap_romstage.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 1168a170c1cd..97bb3bbbeb09 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -29,7 +29,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index d7a6aee85060..f7821f6b6904 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index d7a6aee85060..f7821f6b6904 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index c90f4e06ad93..f097227f0f8d 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 41abd95ca9a3..9821a2fa3acb 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -21,12 +21,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/bd82x6x/pch.h> #include <ec/quanta/ene_kb3940q/ec.h> diff --git a/src/mainboard/google/butterfly/mainboard_smi.c b/src/mainboard/google/butterfly/mainboard_smi.c index 4e02a3cd7f4a..e2f00e17c968 100644 --- a/src/mainboard/google/butterfly/mainboard_smi.c +++ b/src/mainboard/google/butterfly/mainboard_smi.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 13cd45427c69..5e2b713a41e3 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -24,7 +24,6 @@ #include <timestamp.h> #include <arch/byteorder.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 04f68a9b1a16..4ab5017f5295 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -20,12 +20,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/bd82x6x/pch.h> #include "ec.h" #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index 54cfb01f87c9..a4c4a5035149 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 689d2b52fa00..f20a7226aba6 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -24,7 +24,6 @@ #include <timestamp.h> #include <arch/byteorder.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci.h> #include <device/pci_def.h> #include <device/pnp_def.h> diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index d4054ef86496..5e4549d52f99 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -21,13 +21,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> - -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/bd82x6x/pch.h> #include <ec/compal/ene932/ec.h> diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index fc14b9b04449..9968226f81eb 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -24,7 +24,6 @@ #include <timestamp.h> #include <arch/byteorder.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 6f83fd8f003e..a5f6ba2e3dd7 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index db94cb7f47f4..8c8f3480adcc 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -21,12 +21,8 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> #include <console/console.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/bd82x6x/pch.h> #include "ec.h" diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index f6663de6f6e8..79810466c6d8 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 2f4e1a7a76d8..14820ddc656c 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -24,7 +24,6 @@ #include <timestamp.h> #include <arch/byteorder.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 60ffb19fcd1b..0ae744f91cf3 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -4,7 +4,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 9cd25cf00916..ff20289d657d 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -35,7 +35,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index ac624c09985a..2f78cbd300eb 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -34,7 +34,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include "option_table.h" #include <console/console.h> diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index ce3a95ad0b42..81e1ad26cd35 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 148587d8158d..79eaa0b80e98 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -22,7 +22,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/ibase/mb899/smihandler.c b/src/mainboard/ibase/mb899/smihandler.c index 3e3bee7e6d96..064109b2ef3c 100644 --- a/src/mainboard/ibase/mb899/smihandler.c +++ b/src/mainboard/ibase/mb899/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/nvs.h" diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index e5b315a5544d..e4dea5f3aa82 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index b4dddd589996..3462fcb1526b 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/iei/juki-511p/romstage.c b/src/mainboard/iei/juki-511p/romstage.c index 353898e5dbb0..8b26b40e6a80 100644 --- a/src/mainboard/iei/juki-511p/romstage.c +++ b/src/mainboard/iei/juki-511p/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "superio/winbond/w83977f/early_serial.c" diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 293e90f9540f..fbc6395d88e0 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/iei/nova4899r/romstage.c b/src/mainboard/iei/nova4899r/romstage.c index 2a5bcac75f45..174953d9c643 100644 --- a/src/mainboard/iei/nova4899r/romstage.c +++ b/src/mainboard/iei/nova4899r/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "superio/winbond/w83977tf/early_serial.c" diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 6a1bc26150ee..9baf3568f76b 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -20,12 +20,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/gpio.h> diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/mainboard_smi.c index ecfc3851fbdb..e543494b252e 100644 --- a/src/mainboard/intel/baskingridge/mainboard_smi.c +++ b/src/mainboard/intel/baskingridge/mainboard_smi.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/lynxpoint/nvs.h> diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index a4cb3b2ac1d0..a37f6053253e 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -22,7 +22,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/intel/d945gclf/smihandler.c b/src/mainboard/intel/d945gclf/smihandler.c index dbd1a81a647f..0643ad944fa7 100644 --- a/src/mainboard/intel/d945gclf/smihandler.c +++ b/src/mainboard/intel/d945gclf/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/nvs.h" diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 95ad59f9d42e..3aeb71c242bd 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -23,7 +23,6 @@ #include <delay.h> #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 1c5913a4a24d..8e6a732c8ed6 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -20,12 +20,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/bd82x6x/pch.h> #ifndef __PRE_RAM__ diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 4fda2d825288..88bcced67c98 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -23,7 +23,6 @@ #include <lib.h> #include <timestamp.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/intel/emeraldlake2/smihandler.c b/src/mainboard/intel/emeraldlake2/smihandler.c index acc1fde93d69..ba76eb8bbff4 100644 --- a/src/mainboard/intel/emeraldlake2/smihandler.c +++ b/src/mainboard/intel/emeraldlake2/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/intel/jarrell/jarrell_fixups.c b/src/mainboard/intel/jarrell/jarrell_fixups.c index 1261e61046fd..9a5774679bc5 100644 --- a/src/mainboard/intel/jarrell/jarrell_fixups.c +++ b/src/mainboard/intel/jarrell/jarrell_fixups.c @@ -1,4 +1,4 @@ -#include <arch/romcc_io.h> +#include <arch/io.h> static void mch_reset(void) { diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index 784e7df3e6db..c6f014c08ba6 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index d6bbc5a61997..0cab9bdeeddc 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index d77108f4398d..71c5f38d8fad 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include "drivers/pc80/udelay_io.c" diff --git a/src/mainboard/intel/wtm1/chromeos.c b/src/mainboard/intel/wtm1/chromeos.c index 1864754e8898..8142e6541d95 100644 --- a/src/mainboard/intel/wtm1/chromeos.c +++ b/src/mainboard/intel/wtm1/chromeos.c @@ -20,12 +20,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/lynxpoint/pch.h> #ifndef __PRE_RAM__ diff --git a/src/mainboard/intel/wtm1/mainboard_smi.c b/src/mainboard/intel/wtm1/mainboard_smi.c index 281e06168764..3ffc68441d94 100644 --- a/src/mainboard/intel/wtm1/mainboard_smi.c +++ b/src/mainboard/intel/wtm1/mainboard_smi.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/lynxpoint/nvs.h> diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 1864754e8898..8142e6541d95 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -20,12 +20,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/lynxpoint/pch.h> #ifndef __PRE_RAM__ diff --git a/src/mainboard/intel/wtm2/mainboard_smi.c b/src/mainboard/intel/wtm2/mainboard_smi.c index 281e06168764..3ffc68441d94 100644 --- a/src/mainboard/intel/wtm2/mainboard_smi.c +++ b/src/mainboard/intel/wtm2/mainboard_smi.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/lynxpoint/nvs.h> diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c index 4e37811b46d9..342e6f14cb61 100644 --- a/src/mainboard/intel/xe7501devkit/romstage.c +++ b/src/mainboard/intel/xe7501devkit/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <arch/cpu.h> #include <stdlib.h> diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index 83ae65743058..39fce07e6093 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/iwave/iWRainbowG6/smihandler.c b/src/mainboard/iwave/iWRainbowG6/smihandler.c index fc4defb096c5..f2fb1ec9d149 100644 --- a/src/mainboard/iwave/iWRainbowG6/smihandler.c +++ b/src/mainboard/iwave/iWRainbowG6/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/nvs.h" // FIXME: this should point to its own copy of nvs diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index bb235d683d95..6944df052361 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -8,7 +8,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 27152a68d9e4..940e8a65e7d0 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -8,7 +8,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 5ac850849489..bab77604612d 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -8,7 +8,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c index 132a5a6fd018..928fcef992d4 100644 --- a/src/mainboard/jetway/j7f24/romstage.c +++ b/src/mainboard/jetway/j7f24/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/via/cn700/raminit.h" diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index f87013c0bb17..c55efa9f69a3 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -32,7 +32,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index df25fd47d945..03b24d84f4eb 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -23,7 +23,6 @@ #include <string.h> #include <lib.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/kontron/986lcd-m/smihandler.c b/src/mainboard/kontron/986lcd-m/smihandler.c index 3e3bee7e6d96..064109b2ef3c 100644 --- a/src/mainboard/kontron/986lcd-m/smihandler.c +++ b/src/mainboard/kontron/986lcd-m/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/nvs.h" diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 62e02f474b03..084e55eb6901 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -28,7 +28,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index 929e934b8c83..9a7314d6008e 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <lib.h> diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 426286d0df76..9921457e4df5 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -23,7 +23,6 @@ #include <device/device.h> #include <arch/io.h> #include <delay.h> -#include <arch/io.h> #include "dock.h" #include "superio/nsc/pc87384/pc87384.h" #include "ec/acpi/ec.h" diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 046e354c5f61..5e11613c5c62 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -25,7 +25,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index 6ea503776d97..f4bad8b58123 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/nvs.h" diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index ee080ea70a8f..8d5f9222752f 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -25,7 +25,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index c0d8440d4723..5a7130fe5fdd 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/nvs.h" diff --git a/src/mainboard/lippert/frontrunner-af/reset.c b/src/mainboard/lippert/frontrunner-af/reset.c index 5958e772ddc6..bb2482b57b42 100644 --- a/src/mainboard/lippert/frontrunner-af/reset.c +++ b/src/mainboard/lippert/frontrunner-af/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 14a003af4fae..0e1b1340fb09 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/lippert/toucan-af/reset.c b/src/mainboard/lippert/toucan-af/reset.c index 5958e772ddc6..bb2482b57b42 100644 --- a/src/mainboard/lippert/toucan-af/reset.c +++ b/src/mainboard/lippert/toucan-af/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index fcec303c8d42..043af8535370 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index a908aca65081..f597b269f28a 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index e68a59ee1ba0..67fbdc7ee570 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index f52c427ebdfa..f1f4a67af0a6 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index f1c624dfd36a..c965d9464581 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/msi/ms7260/ap_romstage.c b/src/mainboard/msi/ms7260/ap_romstage.c index 31f56c786752..f0a3dc4af529 100644 --- a/src/mainboard/msi/ms7260/ap_romstage.c +++ b/src/mainboard/msi/ms7260/ap_romstage.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include "lib/uart8259.c" diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 9d3f85fdd7b7..6ca0003f044e 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -30,7 +30,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 7bf9c906e841..4910fe563966 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -29,7 +29,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 53fbaf4f2c51..e766bd7a64d4 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index ff15805c7a35..00b794088900 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -28,7 +28,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index ae522d2265df..7af39e478980 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -9,7 +9,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c index 95f3139c5821..627a04742d4d 100644 --- a/src/mainboard/nokia/ip530/romstage.c +++ b/src/mainboard/nokia/ip530/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c index 204ce0b8e7c5..005de7bed683 100644 --- a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include "lib/uart8250.c" diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index ed257257deab..a63e85118916 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -29,7 +29,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 5c80ee888ac1..113eb26e3882 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 3a8209a92c41..aa1a8563ac51 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index 71eefa17bec7..705803d95524 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include "drivers/pc80/udelay_io.c" #include <console/console.h> diff --git a/src/mainboard/rca/rm4100/smihandler.c b/src/mainboard/rca/rm4100/smihandler.c index 8cfefaebe34a..708e5c2eedd7 100644 --- a/src/mainboard/rca/rm4100/smihandler.c +++ b/src/mainboard/rca/rm4100/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index d75d33f50b31..ab200d206187 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -24,7 +24,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/roda/rk886ex/smihandler.c b/src/mainboard/roda/rk886ex/smihandler.c index 6736ace09a26..147051145cea 100644 --- a/src/mainboard/roda/rk886ex/smihandler.c +++ b/src/mainboard/roda/rk886ex/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/nvs.h" diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index c6ca078dc1b3..56eea84f0d03 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -24,7 +24,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> diff --git a/src/mainboard/roda/rk9/smihandler.c b/src/mainboard/roda/rk9/smihandler.c index 8a87cd993b72..fe68c4b5e58c 100644 --- a/src/mainboard/roda/rk9/smihandler.c +++ b/src/mainboard/roda/rk9/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/i82801ix/nvs.h> diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 67a79f002892..2716bf276757 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -20,12 +20,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 67004c70aaf7..b941021f9e87 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -23,7 +23,6 @@ #include <lib.h> #include <timestamp.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <arch/byteorder.h> #include <device/pci_def.h> #include <device/pnp_def.h> diff --git a/src/mainboard/samsung/lumpy/smihandler.c b/src/mainboard/samsung/lumpy/smihandler.c index 4e73a5793813..9306a021180b 100644 --- a/src/mainboard/samsung/lumpy/smihandler.c +++ b/src/mainboard/samsung/lumpy/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 42227357dd6f..a408fd923ba5 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -20,12 +20,8 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include <southbridge/intel/bd82x6x/pch.h> #define GPIO_SPI_WP 68 diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 1fad9493c655..dda3ab53019a 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -24,7 +24,6 @@ #include <timestamp.h> #include <arch/byteorder.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c index 5eda0a1072e6..5c3e1b3a1ffb 100644 --- a/src/mainboard/samsung/stumpy/smihandler.c +++ b/src/mainboard/samsung/stumpy/smihandler.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 108b76231b0f..8198c6cf1b46 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -33,7 +33,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index c4bb23cb141b..632a3117a56a 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index d92739667731..d8dd781add64 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c index a85c1820c31a..ed2d16a78137 100644 --- a/src/mainboard/supermicro/h8dme/ap_romstage.c +++ b/src/mainboard/supermicro/h8dme/ap_romstage.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 1d303a19b7cb..7ad9ec857756 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c index 351898ef51ba..8008bb25c91a 100644 --- a/src/mainboard/supermicro/h8dmr/ap_romstage.c +++ b/src/mainboard/supermicro/h8dmr/ap_romstage.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index dca9248f1802..0a89e0d6c145 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -29,7 +29,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 03b39cc5b29b..c6792d3be2b6 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -28,7 +28,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c index 178a788214d8..2fbe70af95fb 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c @@ -25,7 +25,6 @@ #include "heapManager.h" #include <northbridge/amd/agesa/family15/dimmSpd.h> #include <arch/io.h> -#include <arch/romcc_io.h> #ifdef __PRE_RAM__ /* These defines are used to select the appropriate socket for the SPD read diff --git a/src/mainboard/supermicro/h8qgi/reset.c b/src/mainboard/supermicro/h8qgi/reset.c index 46f97ec071a6..7a96aa45957a 100644 --- a/src/mainboard/supermicro/h8qgi/reset.c +++ b/src/mainboard/supermicro/h8qgi/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index e415bf6d6234..45422bbfbbca 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -21,7 +21,6 @@ #include <reset.h> #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 3725db480c56..c2ccb01d4711 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -28,7 +28,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/supermicro/h8scm/reset.c b/src/mainboard/supermicro/h8scm/reset.c index 46f97ec071a6..7a96aa45957a 100644 --- a/src/mainboard/supermicro/h8scm/reset.c +++ b/src/mainboard/supermicro/h8scm/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 2a988bbdfc0e..3219fdafe542 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -21,7 +21,6 @@ #include <reset.h> #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 259302bbfa04..4ce9b7422c8a 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -31,7 +31,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index dda5817335ab..f57adafe023f 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 37fd2e43d73d..071bb35036cb 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index c9db699a722f..c6350e8e11bf 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 55e1ee7c2d11..9c61d60642be 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index 65bfdb2d5eb2..7cfe818d7093 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c index 43ba238430cd..fa7341231f10 100644 --- a/src/mainboard/supermicro/x7db8/romstage.c +++ b/src/mainboard/supermicro/x7db8/romstage.c @@ -23,7 +23,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 8bb0ea3e246c..5588d8e88b00 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 5ca1dcef9e0e..b9969aaa6f7c 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c index b9b2f1772bcd..680618729659 100644 --- a/src/mainboard/technologic/ts5300/romstage.c +++ b/src/mainboard/technologic/ts5300/romstage.c @@ -8,7 +8,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/televideo/tc7020/romstage.c b/src/mainboard/televideo/tc7020/romstage.c index e887a293cdfb..053da1775383 100644 --- a/src/mainboard/televideo/tc7020/romstage.c +++ b/src/mainboard/televideo/tc7020/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/amd/gx1/raminit.c" diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index ca4813f2d6a9..1e05d6336d21 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <arch/llshell.h> #include "drivers/pc80/udelay_io.c" diff --git a/src/mainboard/thomson/ip1000/smihandler.c b/src/mainboard/thomson/ip1000/smihandler.c index 8cfefaebe34a..708e5c2eedd7 100644 --- a/src/mainboard/thomson/ip1000/smihandler.c +++ b/src/mainboard/thomson/ip1000/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c index 1d27da312465..8e901b21f8a1 100644 --- a/src/mainboard/tyan/s1846/romstage.c +++ b/src/mainboard/tyan/s1846/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index 2bbbf341b727..4e71559a6217 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index 4f14eab8ac2d..5e62f336a026 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index 68422f317eb8..d35c65aa64be 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 20d829cfa483..5f3079643f86 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index b75e387d11ed..404c2df41d34 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 20d829cfa483..5f3079643f86 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index 1e41d7455b30..00dff67b2b4e 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index c57948fac5e6..7a28e80175d5 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 443ded02ada6..8f98e2cf6c09 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index 1b5d21dfcefe..bc6763b8730d 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2912/ap_romstage.c b/src/mainboard/tyan/s2912/ap_romstage.c index 7d9c4b1d06c0..e22d2a5af439 100644 --- a/src/mainboard/tyan/s2912/ap_romstage.c +++ b/src/mainboard/tyan/s2912/ap_romstage.c @@ -26,7 +26,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include "console/console.c" diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index a65b55026767..3cb817630373 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -29,7 +29,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index a2b344c98a92..11394c766eb5 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -28,7 +28,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index bd9c747bf1e9..23efa1089957 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index 363f3bb88924..e21cca384cd4 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c index 8cb5b5c98cf2..0d6e175f5adc 100644 --- a/src/mainboard/tyan/s8226/BiosCallOuts.c +++ b/src/mainboard/tyan/s8226/BiosCallOuts.c @@ -25,7 +25,6 @@ #include "heapManager.h" #include <northbridge/amd/agesa/family15/dimmSpd.h> #include <arch/io.h> -#include <arch/romcc_io.h> #ifdef __PRE_RAM__ /* These defines are used to select the appropriate socket for the SPD read diff --git a/src/mainboard/tyan/s8226/reset.c b/src/mainboard/tyan/s8226/reset.c index 46f97ec071a6..7a96aa45957a 100644 --- a/src/mainboard/tyan/s8226/reset.c +++ b/src/mainboard/tyan/s8226/reset.c @@ -17,10 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index 02f0c3727dd4..ee16ceb57f34 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -21,7 +21,6 @@ #include <reset.h> #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 6995f43c3f12..2d780dbedd98 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index a42484149c86..ebe6a503a1e5 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -3,7 +3,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index a7dcd72b7688..1936052537cd 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -29,7 +29,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include <lib.h> diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index 6f5afab5a612..568dab566725 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "northbridge/via/cn400/raminit.h" diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c index fd053b6bc97a..b1e6c541699a 100644 --- a/src/mainboard/via/epia/romstage.c +++ b/src/mainboard/via/epia/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 5916971473f2..0728154735cc 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index 3fc7091243a8..e1532be14fa5 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include <lib.h> diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c index 612004a7eb24..de1b7d1907a9 100644 --- a/src/northbridge/amd/amdfam10/bootblock.c +++ b/src/northbridge/amd/amdfam10/bootblock.c @@ -1,5 +1,4 @@ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/northbridge/amd/amdk8/bootblock.c b/src/northbridge/amd/amdk8/bootblock.c index b5395bbd9f3a..3a185a6581fc 100644 --- a/src/northbridge/amd/amdk8/bootblock.c +++ b/src/northbridge/amd/amdk8/bootblock.c @@ -1,5 +1,4 @@ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 9ad342367c25..22d74c2c16b7 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -67,7 +67,7 @@ #include <device/pci_ids.h> #include <device/hypertransport_def.h> #include <stdlib.h> -#include "arch/romcc_io.h" +#include <arch/io.h> #include <pc80/mc146818rtc.h> #if CONFIG_HAVE_OPTION_TABLE #include "option_table.h" diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c index 87569a598153..3d6ca2a25e46 100644 --- a/src/northbridge/intel/e7505/debug.c +++ b/src/northbridge/intel/e7505/debug.c @@ -3,7 +3,6 @@ #include <console/console.h> #include <stdlib.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <spd.h> #include "raminit.h" diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 9fba60283359..ae02a7c3d063 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -15,7 +15,6 @@ #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <arch/cpu.h> #include <stdlib.h> #include <console/console.h> diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index 09a166d82fd0..052c5177817c 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include "gm45.h" void gm45_early_init(void) diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index f3902beb5d9c..fccb97f6120d 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -21,7 +21,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include "gm45.h" void gm45_early_reset(void/*const timings_t *const timings*/) diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index c07fdfc26b71..d54ee41f83aa 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -22,7 +22,6 @@ #include <stdint.h> #include <stddef.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 89770ee71b97..e40954adec34 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -23,7 +23,6 @@ #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <arch/acpi.h> diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 6b42e15d0cae..39791a62b865 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -23,7 +23,6 @@ #include <stddef.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> diff --git a/src/northbridge/intel/gm45/pm.c b/src/northbridge/intel/gm45/pm.c index 32a5ba7b96b6..b9ac7f05f155 100644 --- a/src/northbridge/intel/gm45/pm.c +++ b/src/northbridge/intel/gm45/pm.c @@ -23,7 +23,6 @@ #include <stddef.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 1da9e87ed138..9e54c1000093 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -19,9 +19,11 @@ * MA 02110-1301 USA */ +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> #include "gm45.h" diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 68c81206e171..d607f84e1075 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -22,7 +22,6 @@ #include <stdint.h> #include <arch/cpu.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <spd.h> diff --git a/src/northbridge/intel/gm45/thermal.c b/src/northbridge/intel/gm45/thermal.c index a74bcc5e61be..c2ab2a5f8536 100644 --- a/src/northbridge/intel/gm45/thermal.c +++ b/src/northbridge/intel/gm45/thermal.c @@ -23,7 +23,6 @@ #include <stddef.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <spd.h> diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 35f357f57fb0..743007e157e6 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -1,5 +1,4 @@ #include <arch/io.h> -#include <arch/romcc_io.h> /* Just re-define this instead of including haswell.h. It blows up romcc. */ #define PCIEXBAR 0x60 diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index a94c0ce6f013..5b364189e99a 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -22,7 +22,6 @@ #include <stdlib.h> #include <console/console.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <elog.h> #include "haswell.h" diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 58052f9952bd..457f4af0fbcd 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include "haswell.h" diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 1439200de94c..9a9bb1c09f09 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -21,7 +21,6 @@ #include <string.h> #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 9a141b6940df..8bb4a05fbc1d 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -22,9 +22,7 @@ #include <string.h> #include "southbridge/intel/lynxpoint/pch.h" #include <arch/io.h> -#include <arch/io.h> #include <cpu/x86/msr.h> -#include <arch/romcc_io.h> #include "haswell.h" static void report_cpu_info(void) diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c index ef2f45c4dac0..ef9d51382a63 100644 --- a/src/northbridge/intel/i440bx/debug.c +++ b/src/northbridge/intel/i440bx/debug.c @@ -1,6 +1,5 @@ #include <console/console.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <spd.h> #include "raminit.h" #include <spd.h> diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 7472cc994ba3..e3cfbdf25688 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -24,7 +24,6 @@ #include <stdint.h> #include <stdlib.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> #include "i440bx.h" diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index 3c913cf66c1d..48499da4f33a 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -21,7 +21,6 @@ #include "raminit.h" #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h index d3fa16a6ef4e..aa140928db9d 100644 --- a/src/northbridge/intel/i5000/raminit.h +++ b/src/northbridge/intel/i5000/raminit.h @@ -24,7 +24,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #define I5000_MAX_BRANCH 2 #define I5000_MAX_CHANNEL 2 diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c index 88adc24ab18e..c3e4fb99e6ef 100644 --- a/src/northbridge/intel/i82810/debug.c +++ b/src/northbridge/intel/i82810/debug.c @@ -1,6 +1,5 @@ #include <console/console.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <spd.h> #include "i82810.h" #include "raminit.h" diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c index 6a85221d7f47..2c379e7865e7 100644 --- a/src/northbridge/intel/i82810/raminit.c +++ b/src/northbridge/intel/i82810/raminit.c @@ -24,7 +24,6 @@ #include <delay.h> #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> #include "i82810.h" diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c index 37b138a6da5e..e4d93cfe6992 100644 --- a/src/northbridge/intel/i82830/smihandler.c +++ b/src/northbridge/intel/i82830/smihandler.c @@ -22,7 +22,6 @@ #include <types.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index 859a1ef6137e..e47f762fb6ec 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -22,7 +22,6 @@ #include <spd.h> #include <lib.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> #include "i945.h" diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 12e320b834cb..d91930fe1646 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -21,7 +21,6 @@ #include <stdlib.h> #include <console/console.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include "i945.h" #include "pcie_config.c" diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index bbd652820f2d..b1a0684b8e1c 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -23,7 +23,7 @@ #include <pc80/mc146818rtc.h> #include <spd.h> #include <string.h> -#include <arch/romcc_io.h> +#include <arch/io.h> #include "raminit.h" #include "i945.h" #include <cbmem.h> diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index fc10d34dd242..c2d4909f0601 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -22,7 +22,6 @@ #include <stdlib.h> #include <console/console.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <elog.h> #include "sandybridge.h" diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 81512e7e6367..0fa8d1a8a451 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <stdlib.h> #include "pcie_config.c" #include "sandybridge.h" diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 7597b0258d87..78eedb89dbc6 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -21,7 +21,6 @@ #include <string.h> #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <cbmem.h> #include <arch/cbfs.h> #include <cbfs.h> diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index 6e96c94d0ad5..cc748415f93b 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -22,7 +22,6 @@ #include <string.h> #include "southbridge/intel/bd82x6x/pch.h" #include <arch/io.h> -#include <arch/romcc_io.h> #include "sandybridge.h" static void report_cpu_info(void) diff --git a/src/northbridge/intel/sch/port_access.c b/src/northbridge/intel/sch/port_access.c index d3ba70db03e5..c73f7098e7da 100644 --- a/src/northbridge/intel/sch/port_access.c +++ b/src/northbridge/intel/sch/port_access.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> diff --git a/src/northbridge/via/cx700/early_serial.c b/src/northbridge/via/cx700/early_serial.c index cde0b31dc57e..ae5929520093 100644 --- a/src/northbridge/via/cx700/early_serial.c +++ b/src/northbridge/via/cx700/early_serial.c @@ -21,7 +21,7 @@ * Enable the serial devices on the VIA CX700 */ -#include <arch/romcc_io.h> +#include <arch/io.h> static void cx700_writepnpaddr(u8 val) { diff --git a/src/northbridge/via/vx800/early_serial.c b/src/northbridge/via/vx800/early_serial.c index b6f58ac5808d..b3ebde14333a 100644 --- a/src/northbridge/via/vx800/early_serial.c +++ b/src/northbridge/via/vx800/early_serial.c @@ -20,7 +20,7 @@ /* * Enable the serial devices on the VIA */ -#include <arch/romcc_io.h> +#include <arch/io.h> /* The base address is 0x15c, 0x2e, depending on config bytes */ diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c index 228cc7e3cd1f..7c3fb7ae87db 100644 --- a/src/northbridge/via/vx800/examples/romstage.c +++ b/src/northbridge/via/vx800/examples/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include "console/console.c" #include "lib/ramtest.c" diff --git a/src/northbridge/via/vx800/pci_rawops.h b/src/northbridge/via/vx800/pci_rawops.h index 8e775607bc94..33eebc40ac43 100644 --- a/src/northbridge/via/vx800/pci_rawops.h +++ b/src/northbridge/via/vx800/pci_rawops.h @@ -22,7 +22,7 @@ #define NORTHBRIDGE_VIA_VX800_PCI_RAWOPS_H #include <stdint.h> -#include <arch/romcc_io.h> +#include <arch/io.h> struct VIA_PCI_REG_INIT_TABLE { u8 ChipRevisionStart; diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 23be1625073f..65810facf3e7 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 00ca7c67cce1..a0319abdf933 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -21,8 +21,7 @@ #define _HUDSON_EARLY_SETUP_C_ #include <stdint.h> -#include <arch/io.h> /* inl, outl */ -#include <arch/romcc_io.h> /* device_t */ +#include <arch/io.h> #include <arch/acpi.h> #include <console/console.h> #include <reset.h> diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index e1e885c4a189..c74ac9ac6145 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -18,7 +18,6 @@ */ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "hudson.h" diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c index c48aaeb9afd7..315a0653807f 100644 --- a/src/southbridge/amd/agesa/hudson/reset.c +++ b/src/southbridge/amd/agesa/hudson/reset.c @@ -17,11 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <reset.h> +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <arch/io.h> -#include <arch/romcc_io.h> +#include <reset.h> -#include "../../../northbridge/amd/amdk8/reset_test.c" +#include <northbridge/amd/amdk8/reset_test.c> void hard_reset(void) { diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index 2df1fb9f07b5..ba3dc431a046 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */ diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c index 8d77d22ce35d..fc7f3c52cc57 100644 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -19,8 +19,6 @@ #include <arch/io.h> -#include <arch/romcc_io.h> - #if CONFIG_CONSOLE_POST diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index d9ce75aed3ff..13c6379def05 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -17,12 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -//#include <config.h> #include <stdint.h> #include <device/pci_ids.h> -#include <arch/io.h> /* inl, outl */ -#include <arch/romcc_io.h> /* device_t */ +#include <arch/io.h> #include "Platform.h" #include "sb_cimx.h" #include "sb700_cfg.h" /*sb700_cimx_config*/ @@ -30,7 +27,6 @@ #include <console/loglevel.h> #include "smbus.h" - #if CONFIG_RAMINIT_SYSINFO /** * @brief Get SouthBridge device number diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index d21b4fdbfd8c..ac9351e4c21d 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> static void enable_rom(void) { diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 33afdcfe7afe..83087f5527e5 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -17,19 +17,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -//#include <config.h> #include <stdint.h> #include <device/pci_ids.h> #include <arch/io.h> /* inl, outl */ -#include <arch/romcc_io.h> /* device_t */ #include <arch/acpi.h> #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ #include "cbmem.h" - #if CONFIG_RAMINIT_SYSINFO /** * @brief Get SouthBridge device number diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index c88a9fa38c97..106f66473872 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -17,10 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include <arch/io.h> -#include <arch/romcc_io.h> - #if CONFIG_CONSOLE_POST diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index 5acbfa03fed5..d6036ddd19f5 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -17,19 +17,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -//#include <config.h> +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <stdint.h> #include <device/pci_ids.h> -#include <arch/io.h> /* inl, outl */ -#include <arch/romcc_io.h> /* device_t */ +#include <arch/io.h> #include "SbPlatform.h" #include "SbEarly.h" #include <console/console.h> #include <console/loglevel.h> #include "smbus.h" - /** * @brief Get SouthBridge device number * @param[in] bus target bus number @@ -39,13 +38,13 @@ u32 get_sbdn(u32 bus) { device_t dev; - printk(BIOS_INFO, "SB900 - Early.c - get_sbdn - Start.\n"); - //dev = PCI_DEV(bus, 0x14, 0); - dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_ATI_SB900_SM), - bus); + printk(BIOS_SPEW, "SB900 - Early.c - get_sbdn - Start.\n"); + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_ATI_SB900_SM), bus); + + printk(BIOS_SPEW, "SB900 - Early.c - get_sbdn - End.\n"); - printk(BIOS_INFO, "SB900 - Early.c - get_sbdn - End.\n"); return (dev >> 15) & 0x1f; } @@ -59,7 +58,7 @@ void sb_poweron_init(void) AMDSBCFG sb_early_cfg; u8 data; - printk(BIOS_INFO, "SB900 - Early.c - sb_poweron_init - Start.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_poweron_init - Start.\n"); //Enable/Disable PCI Bridge Device 14 Function 4. outb(0xEA, 0xCD6); @@ -77,7 +76,7 @@ void sb_poweron_init(void) //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, // VerifyImage() will fail, LocateImage() take minitues to find the image. sbPowerOnInit(&sb_early_cfg); - printk(BIOS_INFO, "SB900 - Early.c - sb_poweron_init - End.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_poweron_init - End.\n"); } /** @@ -88,7 +87,7 @@ void sb_before_pci_init(void) { AMDSBCFG sb_early_cfg; - printk(BIOS_INFO, "SB900 - Early.c - sb_before_pci_init - Start.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_before_pci_init - Start.\n"); sb900_cimx_config(&sb_early_cfg); //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; //AmdSbDispatcher(&sb_early_cfg); @@ -96,14 +95,14 @@ void sb_before_pci_init(void) //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, // VerifyImage() will fail, LocateImage() take minitues to find the image. sbBeforePciInit(&sb_early_cfg); - printk(BIOS_INFO, "SB900 - Early.c - sb_before_pci_init - End.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_before_pci_init - End.\n"); } void sb_After_Pci_Init(void) { AMDSBCFG sb_early_cfg; - printk(BIOS_INFO, "SB900 - Early.c - sb_After_Pci_Init - Start.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - Start.\n"); sb900_cimx_config(&sb_early_cfg); //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; //AmdSbDispatcher(&sb_early_cfg); @@ -111,14 +110,14 @@ void sb_After_Pci_Init(void) //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, // VerifyImage() will fail, LocateImage() take minitues to find the image. sbAfterPciInit(&sb_early_cfg); - printk(BIOS_INFO, "SB900 - Early.c - sb_After_Pci_Init - End.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - End.\n"); } void sb_Mid_Post_Init(void) { AMDSBCFG sb_early_cfg; - printk(BIOS_INFO, "SB900 - Early.c - sb_Mid_Post_Init - Start.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_Mid_Post_Init - Start.\n"); sb900_cimx_config(&sb_early_cfg); //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; //AmdSbDispatcher(&sb_early_cfg); @@ -126,7 +125,7 @@ void sb_Mid_Post_Init(void) //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, // VerifyImage() will fail, LocateImage() take minitues to find the image. sbMidPostInit(&sb_early_cfg); - printk(BIOS_INFO, "SB900 - Early.c - sb_Mid_Post_Init - End.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_Mid_Post_Init - End.\n"); } void sb_Late_Post(void) @@ -134,7 +133,7 @@ void sb_Late_Post(void) AMDSBCFG sb_early_cfg; u8 data; - printk(BIOS_INFO, "SB900 - Early.c - sb_Late_Post - Start.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_Late_Post - Start.\n"); sb900_cimx_config(&sb_early_cfg); //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; //AmdSbDispatcher(&sb_early_cfg); @@ -160,7 +159,5 @@ void sb_Late_Post(void) outb(data, 0x4D0); } - printk(BIOS_INFO, "SB900 - Early.c - sb_Late_Post - End.\n"); + printk(BIOS_SPEW, "SB900 - Early.c - sb_Late_Post - End.\n"); } - - diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c index e848189df17a..e31a96c8e331 100644 --- a/src/southbridge/amd/sb600/bootblock.c +++ b/src/southbridge/amd/sb600/bootblock.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c index 4130dd5545e7..305362f37d38 100644 --- a/src/southbridge/amd/sb600/enable_usbdebug.c +++ b/src/southbridge/amd/sb600/enable_usbdebug.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "sb600.h" diff --git a/src/southbridge/amd/sb600/reset.c b/src/southbridge/amd/sb600/reset.c index 0c9413699268..0936516c4d8d 100644 --- a/src/southbridge/amd/sb600/reset.c +++ b/src/southbridge/amd/sb600/reset.c @@ -17,11 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <arch/io.h> -#include <arch/romcc_io.h> #include <reset.h> -#include "northbridge/amd/amdk8/reset_test.c" +#include <northbridge/amd/amdk8/reset_test.c> void hard_reset(void) { diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index cffa5ca1daf8..c290806911e0 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index bc6f9107d091..a16fc9f2b20b 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -23,7 +23,6 @@ #include <stdint.h> #include <arch/cpu.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/msr.h> @@ -33,7 +32,6 @@ #include "sb700.h" #include "smbus.h" - static void pmio_write(u8 reg, u8 value) { outb(reg, PM_INDEX); diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index a81625343946..2a7fc383e4ce 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "sb700.h" diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index 9203b2bede12..ef4115ecbeaf 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <reset.h> /* hard_reset, soft_rest*/ -#include <arch/io.h> /* inb, outb */ -#include <arch/romcc_io.h> /* pci_read_config32, device_t, PCI_DEV */ +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include <arch/io.h> +#include <reset.h> #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c index 9d90a34ce053..9311b978f952 100644 --- a/src/southbridge/amd/sb800/bootblock.c +++ b/src/southbridge/amd/sb800/bootblock.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index bdb4bde23c1f..f085eabecb73 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -18,7 +18,6 @@ */ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "sb800.h" diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c index c48aaeb9afd7..315a0653807f 100644 --- a/src/southbridge/amd/sb800/reset.c +++ b/src/southbridge/amd/sb800/reset.c @@ -17,11 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <reset.h> +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <arch/io.h> -#include <arch/romcc_io.h> +#include <reset.h> -#include "../../../northbridge/amd/amdk8/reset_test.c" +#include <northbridge/amd/amdk8/reset_test.c> void hard_reset(void) { diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index cc73cec54ff9..65bce13cf155 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/cpu.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/msr.h> #include "sr5650.h" diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index 23ac1ee90c76..166464cfdaeb 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 7f4f577cd6e6..85a940e2dedd 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/x86/tsc.h> #include "pch.h" diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 5b266cc10caf..670e1cedf586 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -21,7 +21,6 @@ #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index a626649e2bef..9de97e7fe22a 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/bd82x6x/early_spi.c b/src/southbridge/intel/bd82x6x/early_spi.c index ddfc4c226196..6f57f637a958 100644 --- a/src/southbridge/intel/bd82x6x/early_spi.c +++ b/src/southbridge/intel/bd82x6x/early_spi.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index bbe792f908f7..f4e526d85f1d 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index be6d480a6232..bcc2f3dad989 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/post_codes.h> #include <northbridge/intel/sandybridge/pcie_config.c> #include "pch.h" diff --git a/src/southbridge/intel/bd82x6x/gpio.c b/src/southbridge/intel/bd82x6x/gpio.c index 25eda9a74cca..39241d609489 100644 --- a/src/southbridge/intel/bd82x6x/gpio.c +++ b/src/southbridge/intel/bd82x6x/gpio.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include "pch.h" #include "gpio.h" diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index b9aff37d5c5e..7fdf9261f8be 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -38,7 +38,6 @@ #include <elog.h> #ifdef __SMM__ -# include <arch/romcc_io.h> # include <northbridge/intel/sandybridge/pcie_config.c> #else # include <device/device.h> diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index b71f7ea12f0a..f79adf59c017 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -38,7 +38,6 @@ #include <elog.h> #ifdef __SMM__ -# include <arch/romcc_io.h> # include <northbridge/intel/sandybridge/pcie_config.c> #else # include <device/device.h> diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index f2c7dc16486f..37a0b6422c21 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -23,7 +23,6 @@ #include <delay.h> #ifdef __SMM__ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #else /* !__SMM__ */ #include <device/device.h> diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 5d5dad1460b6..545e268a9c0b 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -22,7 +22,6 @@ #include <types.h> #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 4303dd0e7a6f..09169b1bc8b9 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -34,7 +34,6 @@ #define min(a, b) ((a)<(b)?(a):(b)) #ifdef __SMM__ -#include <arch/romcc_io.h> #include <northbridge/intel/sandybridge/pcie_config.c> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pcie_read_config8(dev, reg) diff --git a/src/southbridge/intel/bd82x6x/usb_debug.c b/src/southbridge/intel/bd82x6x/usb_debug.c index 607a88c6c08c..79a43bd30885 100644 --- a/src/southbridge/intel/bd82x6x/usb_debug.c +++ b/src/southbridge/intel/bd82x6x/usb_debug.c @@ -25,7 +25,6 @@ #include "pch.h" #ifdef __PRE_RAM__ -#include <arch/romcc_io.h> void enable_usbdebug(unsigned int port) { u32 dbgctl; diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 135cbc0609bc..b350bde6a97e 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> #include "i82371eb.h" diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c index aaf86114e974..a2f055bca700 100644 --- a/src/southbridge/intel/i82371eb/early_pm.c +++ b/src/southbridge/intel/i82371eb/early_pm.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <console/console.h> diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index d0abcf4dfb6f..80a4de9f8085 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801ax/early_smbus.c b/src/southbridge/intel/i82801ax/early_smbus.c index dde9f33933ff..716652a0f4ab 100644 --- a/src/southbridge/intel/i82801ax/early_smbus.c +++ b/src/southbridge/intel/i82801ax/early_smbus.c @@ -21,7 +21,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801bx/early_smbus.c b/src/southbridge/intel/i82801bx/early_smbus.c index 0522e497b3fa..26c9e8505945 100644 --- a/src/southbridge/intel/i82801bx/early_smbus.c +++ b/src/southbridge/intel/i82801bx/early_smbus.c @@ -21,7 +21,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index ca453a103c6a..6f4d4f884663 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 1d306da280f6..61ac901df596 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -21,7 +21,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index fc052068e8ec..b352fcad03b5 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> static void enable_spi_prefetch(void) { diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 7744e719dcb2..b11e4fa16aff 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 9d71fa33623a..f199b84b659f 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -21,7 +21,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/i82801gx/usb_debug.c b/src/southbridge/intel/i82801gx/usb_debug.c index d5a743c28be7..f447f7bb8447 100644 --- a/src/southbridge/intel/i82801gx/usb_debug.c +++ b/src/southbridge/intel/i82801gx/usb_debug.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <usbdebug.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index fc052068e8ec..b352fcad03b5 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> static void enable_spi_prefetch(void) { diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c index c25c2349ae2e..051471934481 100644 --- a/src/southbridge/intel/i82801ix/dmi_setup.c +++ b/src/southbridge/intel/i82801ix/dmi_setup.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> #include <northbridge/intel/gm45/gm45.h> diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index af2e63f67ed9..8849cfa2c87f 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include "i82801ix.h" void i82801ix_early_init(void) diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 74b36e6ba5fe..226afac2d76d 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 4e8edfe615b8..913223b0ab05 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -22,7 +22,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 2770d55cad0b..96291189cd31 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/x86/tsc.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index e41b801a8b37..6b61eac3dba3 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -21,7 +21,6 @@ #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 3709aed63beb..a390d737bc32 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <elog.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index a626649e2bef..9de97e7fe22a 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/lynxpoint/early_spi.c b/src/southbridge/intel/lynxpoint/early_spi.c index ddfc4c226196..6f57f637a958 100644 --- a/src/southbridge/intel/lynxpoint/early_spi.c +++ b/src/southbridge/intel/lynxpoint/early_spi.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index b2e009123e88..ebd5c2c50a4f 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c index 2cece13e17b5..d9bc22531c95 100644 --- a/src/southbridge/intel/lynxpoint/finalize.c +++ b/src/southbridge/intel/lynxpoint/finalize.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/post_codes.h> #include <spi-generic.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/gpio.c b/src/southbridge/intel/lynxpoint/gpio.c index 9d36887dd111..b492068ccda1 100644 --- a/src/southbridge/intel/lynxpoint/gpio.c +++ b/src/southbridge/intel/lynxpoint/gpio.c @@ -20,14 +20,8 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> - -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif - #include "pch.h" #include "gpio.h" diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index 2d2e0576ea6f..a6e4f5c99849 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -20,12 +20,8 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include "pch.h" #include "lp_gpio.h" diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 2e790fc2a5e9..a16879b7573d 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -31,19 +31,14 @@ #include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> +#include <device/device.h> +#include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_def.h> #include <string.h> #include <delay.h> #include <elog.h> -#ifdef __SMM__ -# include <arch/romcc_io.h> -#else -# include <device/device.h> -# include <device/pci.h> -#endif - #include "me.h" #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 49f7df8d521d..203a1bbfb559 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -23,7 +23,6 @@ #include <types.h> #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/lynxpoint/spi.c b/src/southbridge/intel/lynxpoint/spi.c index 123c6a9d6291..eaa17d5e2198 100644 --- a/src/southbridge/intel/lynxpoint/spi.c +++ b/src/southbridge/intel/lynxpoint/spi.c @@ -34,7 +34,6 @@ #define min(a, b) ((a)<(b)?(a):(b)) #ifdef __SMM__ -#include <arch/romcc_io.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pci_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/lynxpoint/usb_debug.c b/src/southbridge/intel/lynxpoint/usb_debug.c index 1cee353e2d8f..d8da7b548446 100644 --- a/src/southbridge/intel/lynxpoint/usb_debug.c +++ b/src/southbridge/intel/lynxpoint/usb_debug.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <usbdebug.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/sch/early_smbus.c b/src/southbridge/intel/sch/early_smbus.c index 9a015041c010..8adc04df47b7 100644 --- a/src/southbridge/intel/sch/early_smbus.c +++ b/src/southbridge/intel/sch/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c index 99ae01877031..bbaf4bb7f95b 100644 --- a/src/southbridge/intel/sch/smihandler.c +++ b/src/southbridge/intel/sch/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/sch/usb_debug.c b/src/southbridge/intel/sch/usb_debug.c index 1986258d7c3e..4189716c0827 100644 --- a/src/southbridge/intel/sch/usb_debug.c +++ b/src/southbridge/intel/sch/usb_debug.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <usbdebug.h> #include <device/pci_def.h> diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c index a8d0cc9e33f0..e2f6bc022d0c 100644 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ b/src/southbridge/nvidia/ck804/bootblock.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE diff --git a/src/southbridge/nvidia/ck804/early_smbus.c b/src/southbridge/nvidia/ck804/early_smbus.c index 993ff2e61860..a8c12a2198c3 100644 --- a/src/southbridge/nvidia/ck804/early_smbus.c +++ b/src/southbridge/nvidia/ck804/early_smbus.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_def.h> #include <device/pci_ids.h> diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c index c4b62e244d51..659fdc68b13a 100644 --- a/src/southbridge/nvidia/ck804/enable_usbdebug.c +++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c @@ -23,7 +23,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "ck804.h" diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index 59a0aaece08b..431c426d042f 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -23,7 +23,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include "mcp55.h" static void mcp55_enable_rom(void) diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c index 4a03a2762bc5..f753c7853891 100644 --- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c @@ -23,7 +23,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "mcp55.h" diff --git a/src/southbridge/rdc/r8610/bootblock.c b/src/southbridge/rdc/r8610/bootblock.c index c87940a495e4..2e5e360d72e3 100644 --- a/src/southbridge/rdc/r8610/bootblock.c +++ b/src/southbridge/rdc/r8610/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> static void bootblock_southbridge_init(void) { diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c index f4cb264472db..ac4919aae8c7 100644 --- a/src/southbridge/sis/sis966/bootblock.c +++ b/src/southbridge/sis/sis966/bootblock.c @@ -25,7 +25,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> #include "sis966.h" diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c index cf19577115b7..78a3838be7ea 100644 --- a/src/southbridge/sis/sis966/enable_usbdebug.c +++ b/src/southbridge/sis/sis966/enable_usbdebug.c @@ -25,7 +25,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> #include "sis966.h" diff --git a/src/southbridge/via/vt8231/enable_rom.c b/src/southbridge/via/vt8231/enable_rom.c index f2d0866dc8d9..618adf8ddf18 100644 --- a/src/southbridge/via/vt8231/enable_rom.c +++ b/src/southbridge/via/vt8231/enable_rom.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> static void vt8231_enable_rom(void) diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c index 98297911c45a..0d920739e649 100644 --- a/src/southbridge/via/vt8237r/bootblock.c +++ b/src/southbridge/via/vt8237r/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> static void bootblock_southbridge_init(void) diff --git a/src/southbridge/via/vt8237r/smihandler.c b/src/southbridge/via/vt8237r/smihandler.c index 357e517994c0..d46c4ec7be03 100644 --- a/src/southbridge/via/vt8237r/smihandler.c +++ b/src/southbridge/via/vt8237r/smihandler.c @@ -22,7 +22,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/via/vt82c686/early_serial.c b/src/southbridge/via/vt82c686/early_serial.c index 8ac79d63b2cd..70b6b545fc0e 100644 --- a/src/southbridge/via/vt82c686/early_serial.c +++ b/src/southbridge/via/vt82c686/early_serial.c @@ -22,7 +22,7 @@ /* This has been ported to the VIA VT82C686(A/B) from the SMSC FDC37M60x * by Corey Osgood. See vt82c686.h for more information. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include <device/pci_ids.h> #include "vt82c686.h" diff --git a/src/superio/fintek/f71805f/early_serial.c b/src/superio/fintek/f71805f/early_serial.c index e774f0c0f990..827f870a3727 100644 --- a/src/superio/fintek/f71805f/early_serial.c +++ b/src/superio/fintek/f71805f/early_serial.c @@ -20,7 +20,7 @@ /* Pre-RAM driver for the Fintek F71805F/FG Super I/O chip. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "f71805f.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f71859/early_serial.c b/src/superio/fintek/f71859/early_serial.c index 6781ad7bd88c..4401714b98b7 100644 --- a/src/superio/fintek/f71859/early_serial.c +++ b/src/superio/fintek/f71859/early_serial.c @@ -20,7 +20,7 @@ /* Pre-RAM driver for the Fintek F71859 Super I/O chip. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "f71859.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f71863fg/early_serial.c b/src/superio/fintek/f71863fg/early_serial.c index bf6c9ab43ee7..5d1cfb715eb1 100644 --- a/src/superio/fintek/f71863fg/early_serial.c +++ b/src/superio/fintek/f71863fg/early_serial.c @@ -20,7 +20,7 @@ /* Pre-RAM driver for the Fintek F71863FG Super I/O chip. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "f71863fg.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f71872/early_serial.c b/src/superio/fintek/f71872/early_serial.c index 55646a4a93c4..af5cdb35451f 100644 --- a/src/superio/fintek/f71872/early_serial.c +++ b/src/superio/fintek/f71872/early_serial.c @@ -20,7 +20,7 @@ /* Pre-RAM driver for the Fintek F71872F/FG Super I/O chip. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "f71872.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f71889/early_serial.c b/src/superio/fintek/f71889/early_serial.c index 4548e1c01ba3..9623cbd2a398 100644 --- a/src/superio/fintek/f71889/early_serial.c +++ b/src/superio/fintek/f71889/early_serial.c @@ -19,7 +19,7 @@ */ #include <stdint.h> -#include <arch/romcc_io.h> +#include <arch/io.h> #include "f71889.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f81865f/f81865f_early_serial.c b/src/superio/fintek/f81865f/f81865f_early_serial.c index 80af5aaaf611..2989b5f911b9 100644 --- a/src/superio/fintek/f81865f/f81865f_early_serial.c +++ b/src/superio/fintek/f81865f/f81865f_early_serial.c @@ -20,7 +20,7 @@ /* Pre-RAM driver for the Fintek F81865F/FG Super I/O chip. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "f81865f.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index 9508bc3ad96a..f95cf8a5333e 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "i3100.h" static void pnp_enter_ext_func_mode(device_t dev) diff --git a/src/superio/ite/it8661f/early_serial.c b/src/superio/ite/it8661f/early_serial.c index 4bc88b15b3e0..ee132fa07743 100644 --- a/src/superio/ite/it8661f/early_serial.c +++ b/src/superio/ite/it8661f/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8661f.h" /* Perform MB PnP setup to put the SIO chip at 0x3f0. */ diff --git a/src/superio/ite/it8671f/early_serial.c b/src/superio/ite/it8671f/early_serial.c index 7b9e1b549182..c2ba6e02a197 100644 --- a/src/superio/ite/it8671f/early_serial.c +++ b/src/superio/ite/it8671f/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8671f.h" /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ diff --git a/src/superio/ite/it8673f/early_serial.c b/src/superio/ite/it8673f/early_serial.c index 61e8effd08dc..987b5e6135da 100644 --- a/src/superio/ite/it8673f/early_serial.c +++ b/src/superio/ite/it8673f/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8673f.h" /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ diff --git a/src/superio/ite/it8705f/early_serial.c b/src/superio/ite/it8705f/early_serial.c index d1e6b4f2119c..ccc92c2dbf96 100644 --- a/src/superio/ite/it8705f/early_serial.c +++ b/src/superio/ite/it8705f/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8705f.h" /* The base address is 0x2e or 0x4e, depending on config bytes. */ diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c index 6cf5afd7331b..51564fce0422 100644 --- a/src/superio/ite/it8712f/early_serial.c +++ b/src/superio/ite/it8712f/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8712f.h" /* The base address is 0x2e or 0x4e, depending on config bytes. */ diff --git a/src/superio/ite/it8716f/early_init.c b/src/superio/ite/it8716f/early_init.c index 8d684b6e615c..cfac2a9cbfc6 100644 --- a/src/superio/ite/it8716f/early_init.c +++ b/src/superio/ite/it8716f/early_init.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8716f.h" void it8716f_disable_dev(device_t dev) diff --git a/src/superio/ite/it8716f/early_serial.c b/src/superio/ite/it8716f/early_serial.c index 55047f8e8b65..02f030449c4b 100644 --- a/src/superio/ite/it8716f/early_serial.c +++ b/src/superio/ite/it8716f/early_serial.c @@ -21,7 +21,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8716f.h" /* The base address is 0x2e or 0x4e, depending on config bytes. */ diff --git a/src/superio/ite/it8718f/early_serial.c b/src/superio/ite/it8718f/early_serial.c index a4335f387eae..308b67cd40e4 100644 --- a/src/superio/ite/it8718f/early_serial.c +++ b/src/superio/ite/it8718f/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8718f.h" /* The base address is 0x2e or 0x4e, depending on config bytes. */ diff --git a/src/superio/ite/it8721f/early_serial.c b/src/superio/ite/it8721f/early_serial.c index 8272ef62787a..20e19b65aa8f 100644 --- a/src/superio/ite/it8721f/early_serial.c +++ b/src/superio/ite/it8721f/early_serial.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "it8721f.h" /* The base address is 0x2e or 0x4e, depending on config bytes. */ diff --git a/src/superio/ite/it8772f/early_serial.c b/src/superio/ite/it8772f/early_serial.c index 8cf459a3a374..8bf2964a50ce 100644 --- a/src/superio/ite/it8772f/early_serial.c +++ b/src/superio/ite/it8772f/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include <device/pnp_def.h> #include "it8772f.h" diff --git a/src/superio/nsc/pc8374/early_init.c b/src/superio/nsc/pc8374/early_init.c index f5e4e80da758..d3f601df12db 100644 --- a/src/superio/nsc/pc8374/early_init.c +++ b/src/superio/nsc/pc8374/early_init.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc8374.h" static void pc8374_enable(u16 iobase, u8 *init) diff --git a/src/superio/nsc/pc87309/early_serial.c b/src/superio/nsc/pc87309/early_serial.c index f6be3ed4ddde..131f0aaeacc7 100644 --- a/src/superio/nsc/pc87309/early_serial.c +++ b/src/superio/nsc/pc87309/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc87309.h" static void pc87309_enable_serial(device_t dev, u16 iobase) diff --git a/src/superio/nsc/pc87351/early_serial.c b/src/superio/nsc/pc87351/early_serial.c index 6f97a76b99b9..c34538fd7cc9 100644 --- a/src/superio/nsc/pc87351/early_serial.c +++ b/src/superio/nsc/pc87351/early_serial.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc87351.h" static void pc87351_enable_serial(device_t dev, u16 iobase) diff --git a/src/superio/nsc/pc87360/early_serial.c b/src/superio/nsc/pc87360/early_serial.c index 657cd6859dc9..da4abdb3307d 100644 --- a/src/superio/nsc/pc87360/early_serial.c +++ b/src/superio/nsc/pc87360/early_serial.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc87360.h" static void pc87360_enable_serial(device_t dev, u16 iobase) diff --git a/src/superio/nsc/pc87366/early_serial.c b/src/superio/nsc/pc87366/early_serial.c index e0bc2c52689a..e173afd632c7 100644 --- a/src/superio/nsc/pc87366/early_serial.c +++ b/src/superio/nsc/pc87366/early_serial.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc87366.h" static void pc87366_enable_serial(device_t dev, u16 iobase) diff --git a/src/superio/nsc/pc87392/early_serial.c b/src/superio/nsc/pc87392/early_serial.c index a485ddbfadc6..6e85fb96b82f 100644 --- a/src/superio/nsc/pc87392/early_serial.c +++ b/src/superio/nsc/pc87392/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc87392.h" static void pc87392_enable_serial(device_t dev, u16 iobase) diff --git a/src/superio/nsc/pc87417/early_init.c b/src/superio/nsc/pc87417/early_init.c index 59f1ab61e827..d1870f9cba30 100644 --- a/src/superio/nsc/pc87417/early_init.c +++ b/src/superio/nsc/pc87417/early_init.c @@ -20,7 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc87417.h" static void pc87417_disable_dev(device_t dev) diff --git a/src/superio/nsc/pc87417/early_serial.c b/src/superio/nsc/pc87417/early_serial.c index 0e87fc576d30..33bae7e071c9 100644 --- a/src/superio/nsc/pc87417/early_serial.c +++ b/src/superio/nsc/pc87417/early_serial.c @@ -20,7 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc87417.h" void pc87417_enable_serial(device_t dev, u16 iobase) diff --git a/src/superio/nsc/pc87427/early_init.c b/src/superio/nsc/pc87427/early_init.c index 512e440c1159..6df1b9f88d34 100644 --- a/src/superio/nsc/pc87427/early_init.c +++ b/src/superio/nsc/pc87427/early_init.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc87427.h" static void pc87427_disable_dev(device_t dev) diff --git a/src/superio/nsc/pc97317/early_serial.c b/src/superio/nsc/pc97317/early_serial.c index 593c22eca2a5..0c215611bc32 100644 --- a/src/superio/nsc/pc97317/early_serial.c +++ b/src/superio/nsc/pc97317/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pc97317.h" #define PM_DEV PNP_DEV(0x2e, PC97317_PM) diff --git a/src/superio/nuvoton/wpcm450/early_init.c b/src/superio/nuvoton/wpcm450/early_init.c index a90f2662e0b1..d95eaaea41e1 100644 --- a/src/superio/nuvoton/wpcm450/early_init.c +++ b/src/superio/nuvoton/wpcm450/early_init.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pnp_def.h> #include "wpcm450.h" diff --git a/src/superio/serverengines/pilot/early_serial.c b/src/superio/serverengines/pilot/early_serial.c index f339d8e272fe..4112901c4da7 100644 --- a/src/superio/serverengines/pilot/early_serial.c +++ b/src/superio/serverengines/pilot/early_serial.c @@ -21,7 +21,7 @@ /* PILOT Super I/O is only based on LPC observation done on factory system. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "pilot.h" /* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ diff --git a/src/superio/smsc/fdc37m60x/early_serial.c b/src/superio/smsc/fdc37m60x/early_serial.c index a3539b15d156..38cb0f8f27ff 100644 --- a/src/superio/smsc/fdc37m60x/early_serial.c +++ b/src/superio/smsc/fdc37m60x/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "fdc37m60x.h" /* The base address is 0x3f0 or 0x370, depending on the SYSOPT pin. */ diff --git a/src/superio/smsc/kbc1100/kbc1100_early_init.c b/src/superio/smsc/kbc1100/kbc1100_early_init.c index e12db31d0fa1..5d74c3230e62 100644 --- a/src/superio/smsc/kbc1100/kbc1100_early_init.c +++ b/src/superio/smsc/kbc1100/kbc1100_early_init.c @@ -19,7 +19,7 @@ /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "kbc1100.h" static inline void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/smsc/lpc47b272/early_serial.c b/src/superio/smsc/lpc47b272/early_serial.c index 54e854c65e52..b2f0d1b72442 100644 --- a/src/superio/smsc/lpc47b272/early_serial.c +++ b/src/superio/smsc/lpc47b272/early_serial.c @@ -20,7 +20,7 @@ /* Pre-RAM driver for SMSC LPC47B272 Super I/O chip. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "lpc47b272.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/smsc/lpc47b397/early_serial.c b/src/superio/smsc/lpc47b397/early_serial.c index 930e41a33165..31d515b5c0a0 100644 --- a/src/superio/smsc/lpc47b397/early_serial.c +++ b/src/superio/smsc/lpc47b397/early_serial.c @@ -20,7 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "lpc47b397.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/smsc/lpc47m10x/early_serial.c b/src/superio/smsc/lpc47m10x/early_serial.c index 99aebbc84d54..fc6efb91d825 100644 --- a/src/superio/smsc/lpc47m10x/early_serial.c +++ b/src/superio/smsc/lpc47m10x/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "lpc47m10x.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/smsc/lpc47m15x/early_serial.c b/src/superio/smsc/lpc47m15x/early_serial.c index bd57a28b7018..7d75baecbec5 100644 --- a/src/superio/smsc/lpc47m15x/early_serial.c +++ b/src/superio/smsc/lpc47m15x/early_serial.c @@ -19,7 +19,7 @@ /* Pre-RAM driver for the SMSC LPC47M15X Super I/O chip */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "lpc47m15x.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c index 6c0276970b88..451628a449e1 100644 --- a/src/superio/smsc/lpc47n217/early_serial.c +++ b/src/superio/smsc/lpc47n217/early_serial.c @@ -20,7 +20,7 @@ /* Pre-RAM driver for SMSC LPC47N217 Super I/O chip. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include <assert.h> #include "lpc47n217.h" diff --git a/src/superio/smsc/lpc47n227/early_serial.c b/src/superio/smsc/lpc47n227/early_serial.c index b20bc80156ab..4aea7c57fc29 100644 --- a/src/superio/smsc/lpc47n227/early_serial.c +++ b/src/superio/smsc/lpc47n227/early_serial.c @@ -20,7 +20,7 @@ /* Pre-RAM driver for SMSC LPC47N227 Super I/O chip. */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "lpc47n227.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c index fc9aaf5eab73..dfacd24aca4a 100644 --- a/src/superio/smsc/sch4037/sch4037_early_init.c +++ b/src/superio/smsc/sch4037/sch4037_early_init.c @@ -18,7 +18,7 @@ */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "sch4037.h" static inline void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index 289d83f1ab63..314ea7541b2f 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -19,7 +19,7 @@ /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "sio1036.h" #ifndef CONFIG_TTYS0_BASE diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c index 85f7b461c108..5e9aadb7e3fb 100644 --- a/src/superio/smsc/smscsuperio/early_serial.c +++ b/src/superio/smsc/smscsuperio/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include <device/pnp_def.h> /* All known/supported SMSC Super I/Os have the same logical device IDs diff --git a/src/superio/winbond/w83627dhg/early_serial.c b/src/superio/winbond/w83627dhg/early_serial.c index 8ea29eaa3625..ec9e81e00a37 100644 --- a/src/superio/winbond/w83627dhg/early_serial.c +++ b/src/superio/winbond/w83627dhg/early_serial.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pnp_def.h> #include <stdint.h> #include "w83627dhg.h" diff --git a/src/superio/winbond/w83627ehg/early_init.c b/src/superio/winbond/w83627ehg/early_init.c index 24cc4517043b..7be5e37ad35f 100644 --- a/src/superio/winbond/w83627ehg/early_init.c +++ b/src/superio/winbond/w83627ehg/early_init.c @@ -20,7 +20,7 @@ */ #include <stdint.h> -#include <arch/romcc_io.h> +#include <arch/io.h> #include "w83627ehg.h" void w83627ehg_disable_dev(device_t dev) diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c index 03e72f3a3322..1a895c6bd9ce 100644 --- a/src/superio/winbond/w83627ehg/early_serial.c +++ b/src/superio/winbond/w83627ehg/early_serial.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "w83627ehg.h" static void pnp_enter_ext_func_mode(device_t dev) diff --git a/src/superio/winbond/w83627hf/early_init.c b/src/superio/winbond/w83627hf/early_init.c index b61922dba871..66b40980a2d9 100644 --- a/src/superio/winbond/w83627hf/early_init.c +++ b/src/superio/winbond/w83627hf/early_init.c @@ -20,7 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "w83627hf.h" void w83627hf_disable_dev(device_t dev) diff --git a/src/superio/winbond/w83627hf/early_serial.c b/src/superio/winbond/w83627hf/early_serial.c index 0e857cfbed33..db2827bfdb93 100644 --- a/src/superio/winbond/w83627hf/early_serial.c +++ b/src/superio/winbond/w83627hf/early_serial.c @@ -21,7 +21,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "w83627hf.h" static void pnp_enter_ext_func_mode(device_t dev) diff --git a/src/superio/winbond/w83627thg/early_serial.c b/src/superio/winbond/w83627thg/early_serial.c index 6803aabb894e..8ba1a308ae14 100644 --- a/src/superio/winbond/w83627thg/early_serial.c +++ b/src/superio/winbond/w83627thg/early_serial.c @@ -20,7 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "w83627thg.h" static void pnp_enter_ext_func_mode(device_t dev) diff --git a/src/superio/winbond/w83627uhg/early_serial.c b/src/superio/winbond/w83627uhg/early_serial.c index 43946bd0d946..bfd08a37669d 100644 --- a/src/superio/winbond/w83627uhg/early_serial.c +++ b/src/superio/winbond/w83627uhg/early_serial.c @@ -18,8 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> -#include <stdint.h> +#include <arch/io.h> #include "w83627uhg.h" static void pnp_enter_ext_func_mode(device_t dev) diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index e26168e80050..e435645453c3 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -18,8 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> -#include <arch/romcc_io.h> +#include <arch/io.h> #include "w83697hf.h" static void pnp_enter_ext_func_mode(device_t dev) diff --git a/src/superio/winbond/w83977f/early_serial.c b/src/superio/winbond/w83977f/early_serial.c index 400cb86b9102..c572dcb9597a 100644 --- a/src/superio/winbond/w83977f/early_serial.c +++ b/src/superio/winbond/w83977f/early_serial.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "w83977f.h" static void pnp_enter_ext_func_mode(device_t dev) diff --git a/src/superio/winbond/w83977tf/early_serial.c b/src/superio/winbond/w83977tf/early_serial.c index 208bc6859cec..c0165155312f 100644 --- a/src/superio/winbond/w83977tf/early_serial.c +++ b/src/superio/winbond/w83977tf/early_serial.c @@ -20,7 +20,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/romcc_io.h> +#include <arch/io.h> #include "w83977tf.h" static void pnp_enter_ext_func_mode(device_t dev) |