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| author | Bora Guvendik <bora.guvendik@intel.com> | 2020-11-25 16:38:08 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-30 08:07:00 +0000 |
| commit | 2821cb498b6d85548e42852b6e1ad25cb648c44d (patch) | |
| tree | 14ebb90a3bfce98da5cad5789fa2c2f884e079d6 /src | |
| parent | c67e3c1a905fea91e8ac0973857ad142b0337a00 (diff) | |
| download | coreboot-2821cb498b6d85548e42852b6e1ad25cb648c44d.tar.gz coreboot-2821cb498b6d85548e42852b6e1ad25cb648c44d.tar.bz2 coreboot-2821cb498b6d85548e42852b6e1ad25cb648c44d.zip | |
include/device/pci_ids.h: Fix device id for gspi2
Device ID for "D18:F6 - GSPI #2" shoud be 0xA0FB
BUG=none
TEST=Boot to OS, verify SSDT
Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I0d814170d24ff1b989eceb1d9ebdf6134df85e2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48060
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/device/pci_ids.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index c123002b759e..51c0abf5f36d 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3563,7 +3563,7 @@ #define PCI_DEVICE_ID_INTEL_TGP_SPI0 0xa0a4 #define PCI_DEVICE_ID_INTEL_TGP_GSPI0 0xa0aa #define PCI_DEVICE_ID_INTEL_TGP_GSPI1 0xa0ab -#define PCI_DEVICE_ID_INTEL_TGP_GSPI2 0x34fb +#define PCI_DEVICE_ID_INTEL_TGP_GSPI2 0xa0fb #define PCI_DEVICE_ID_INTEL_TGP_GSPI3 0xa0fd #define PCI_DEVICE_ID_INTEL_TGP_GSPI4 0xa0fe #define PCI_DEVICE_ID_INTEL_TGP_GSPI5 0xa0de |