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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-25 12:12:34 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-28 10:10:26 +0000 |
| commit | 28c6df73239b6c04c25fba43b072fbb92a348feb (patch) | |
| tree | 6a89f52cd9508a35f66fe6baa1bff48b269f7d4e /src | |
| parent | 307320c23f2c1907ff6cf6fa87608d1155aba05f (diff) | |
| download | coreboot-28c6df73239b6c04c25fba43b072fbb92a348feb.tar.gz coreboot-28c6df73239b6c04c25fba43b072fbb92a348feb.tar.bz2 coreboot-28c6df73239b6c04c25fba43b072fbb92a348feb.zip | |
sb/intel/common: Rename TCO timeout
Rename TCO1_TIMEOUT to TCO_TIMEOUT to match rest of the tree.
Change-Id: Ib136e9b2d0006eb4ceceb298b557644760d1185c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/common/tco.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/common/watchdog.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 3aef48a56bc4..8155479ebf96 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -466,7 +466,7 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO1_STS 0x64 -#define TCO1_TIMEOUT (1 << 3) +#define TCO_TIMEOUT (1 << 3) #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 #define TCO2_STS_SECOND_TO (1 << 1) diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h index 168971e431cd..5bf386f1c286 100644 --- a/src/southbridge/intel/common/tco.h +++ b/src/southbridge/intel/common/tco.h @@ -13,7 +13,7 @@ #define PMBASE_TCO_OFFSET 0x60 #define TCO1_STS 0x04 -#define TCO1_TIMEOUT (1 << 3) +#define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 #define TCO2_STS_SECOND_TO (1 << 1) #define TCO1_CNT 0x08 diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c index a9886916ca47..e22dbfbf6263 100644 --- a/src/southbridge/intel/common/watchdog.c +++ b/src/southbridge/intel/common/watchdog.c @@ -32,7 +32,7 @@ void watchdog_off(void) write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value); /* Clear TCO timeout status. */ - write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT); + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO_TIMEOUT); write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, TCO2_STS_SECOND_TO); printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n"); |