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| author | Sean Rhodes <sean@starlabs.systems> | 2022-07-28 20:50:49 +0100 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-10-06 18:20:47 +0000 |
| commit | 291758ddbaa004f9ca2326b3d9f6b5e37bc663ec (patch) | |
| tree | a5549efecbb09750c70690d4e23b47f9e3cb6da5 /src | |
| parent | e72ff319fd14422d5061c2668dcf41d292ac3473 (diff) | |
| download | coreboot-291758ddbaa004f9ca2326b3d9f6b5e37bc663ec.tar.gz coreboot-291758ddbaa004f9ca2326b3d9f6b5e37bc663ec.tar.bz2 coreboot-291758ddbaa004f9ca2326b3d9f6b5e37bc663ec.zip | |
soc/intel/apollolake/acpi: Add PCIEXBAR to MCHC
The values in this patch were found in the following datasheets:
* 334819 (APL)
* 336561 (GLK)
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I14c5933b9022703c8951da7c6a26eb703258ec37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/northbridge.asl | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index f8023bed9cd7..373d6b8ea432 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -11,8 +11,12 @@ Device (MCHC) OperationRegion (MCHP, PCI_Config, 0x00, 0x100) Field (MCHP, DWordAcc, NoLock, Preserve) { - Offset(0x60), - MCNF, 32, /* PCI MMCONF base */ + Offset (0x60), /* PCIEXBAR (0:0:0:60) + PXEN, 1, /* Enable */ + PXSZ, 2, /* PCI Express Size */ + , 25, + PXBR, 11, /* PCI Express Base Address */ + Offset (0xA8), TUUD, 64, /* Top of Upper Used Memory */ Offset(0xB4), |