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| author | Subrata Banik <subratabanik@google.com> | 2022-07-26 12:48:39 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-07-28 11:13:07 +0000 |
| commit | 2ba4bfef7ed31ff2950ecd6c7269d4148d652764 (patch) | |
| tree | 33df62b4d1ef94c44e2439844fc7ac820e140ae4 /src | |
| parent | 4a12f54654b8b5de32d9a0fca1bb12bcad2d478c (diff) | |
| download | coreboot-2ba4bfef7ed31ff2950ecd6c7269d4148d652764.tar.gz coreboot-2ba4bfef7ed31ff2950ecd6c7269d4148d652764.tar.bz2 coreboot-2ba4bfef7ed31ff2950ecd6c7269d4148d652764.zip | |
soc/intel/gpio: Add new macro for GPP PAD reset type as `Global Reset`
This patch introduces a new macro for GPP PAD reset type as
`Global Reset` as documented in Alder Lake EDS doc 630603.
BUG=b:213293047
TEST=Able to build Google/Kano with this change.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I39428911babc393dd10750801522a00d0b26d3e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/gpio_defs.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index efa960cf8aa8..beff0a0f9b49 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -45,6 +45,11 @@ #define PAD_CFG0_LOGICAL_RESET_DEEP (1U << 30) #define PAD_CFG0_LOGICAL_RESET_PLTRST (2U << 30) #define PAD_CFG0_LOGICAL_RESET_RSMRST (3U << 30) +/* + * Alder Lake PCH onwards a newer bit field has added + * for GPP as `Global Reset` + */ +#define PAD_CFG0_LOGICAL_RESET_GLBRST (3U << 30) /* * Use the fourth bit in IntSel field to indicate gpio |