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| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-11-01 16:36:35 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-12-31 17:35:40 +0100 |
| commit | 3218e794ba567ee7b51f2206e01f86f1d9358358 (patch) | |
| tree | f93d822dfabc944551226fb8933515c568950429 /src | |
| parent | 88357548a20e7850acdd4528b1923d15c728ac09 (diff) | |
| download | coreboot-3218e794ba567ee7b51f2206e01f86f1d9358358.tar.gz coreboot-3218e794ba567ee7b51f2206e01f86f1d9358358.tar.bz2 coreboot-3218e794ba567ee7b51f2206e01f86f1d9358358.zip | |
imgtec/pistachio: memlayout: update GRAM size
GRAM is 421056 bytes. The end of the SRAM region (GRAM plays the role
of SRAM) was placed at a 4K aligned address, resulting in a size of
408KB.
Change-Id: I9fa32ab818d600e7447bcac895e4b8c438f2f99d
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index a0b48b2e6de7..c84de4003188 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -39,7 +39,7 @@ SECTIONS ROMSTAGE(0x1a005000, 40K) VBOOT2_WORK(0x1a00f000, 12K) PRERAM_CBFS_CACHE(0x1a012000, 56K) - SRAM_END(0x1a020000) + SRAM_END(0x1a066000) /* Bootblock executes out of KSEG0 and sets up the identity mapping. * This is identical to SRAM above, and thus also limited 64K and |