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| author | Wisley Chen <wisley.chen@quantatw.com> | 2020-09-02 14:08:22 +0800 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-09-02 23:33:09 +0000 |
| commit | 32c26493fbaaf0a3e44db670f69b3094f4fcd110 (patch) | |
| tree | 592dcaa51e71b0fd90103532dbfe6021ed74995d /src | |
| parent | 456f8dc0a9786541ffb2f4c6baf2f02230870edc (diff) | |
| download | coreboot-32c26493fbaaf0a3e44db670f69b3094f4fcd110.tar.gz coreboot-32c26493fbaaf0a3e44db670f69b3094f4fcd110.tar.bz2 coreboot-32c26493fbaaf0a3e44db670f69b3094f4fcd110.zip | |
mb/google/puff/var/noibat: Update DPTF parameters for noibat
1. Update paramerters form thermal team.
2. Update PL2 Max/Min to 51W/15W.
BUG=b:167494420
BRANCH=puff
TEST=build noibat and verified by thermal team.
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: Id96e681e9a990a1a1eaeb22781b1c60a7369118b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45020
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/hatch/variants/noibat/overridetree.cb | 34 |
1 files changed, 18 insertions, 16 deletions
diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb index de49462d0618..e206ea57e536 100644 --- a/src/mainboard/google/hatch/variants/noibat/overridetree.cb +++ b/src/mainboard/google/hatch/variants/noibat/overridetree.cb @@ -1,4 +1,8 @@ chip soc/intel/cannonlake + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -197,29 +201,27 @@ chip soc/intel/cannonlake chip drivers/intel/dptf ## Active Policy register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(90, 85), - TEMP_PCT(85, 75), - TEMP_PCT(80, 65), - TEMP_PCT(75, 55), - TEMP_PCT(70, 45),}}" + .thresholds={TEMP_PCT(94, 0),}}" register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(50, 85), - TEMP_PCT(47, 75), - TEMP_PCT(45, 65), - TEMP_PCT(42, 55), - TEMP_PCT(39, 45),}}" + .thresholds={TEMP_PCT(65, 90), + TEMP_PCT(52, 80), + TEMP_PCT(50, 70), + TEMP_PCT(48, 60), + TEMP_PCT(46, 50), + TEMP_PCT(44, 40), + TEMP_PCT(42, 0),}}" ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)" ## Critical Policy register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" ## Power Limits Control # PL1 is fixed at 15W, avg over 28-32s interval - # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + # 15-51W PL2 in 1000mW increments, avg over 28-32s interval register "controls.power_limits.pl1" = "{ .min_power = 15000, .max_power = 15000, @@ -227,8 +229,8 @@ chip soc/intel/cannonlake .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200,}" register "controls.power_limits.pl2" = "{ - .min_power = 25000, - .max_power = 64000, + .min_power = 15000, + .max_power = 51000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000,}" |