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| author | Sergii Dmytruk <sergii.dmytruk@3mdeb.com> | 2021-08-21 16:24:02 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-11 20:18:05 +0000 |
| commit | 3a96074441c4e2b28d6d6961b94fec5c4eada8ec (patch) | |
| tree | aa5d68b48b0032f538cd8fa18552ef9c4c245cd5 /src | |
| parent | dba9b54731c000b26334bd31a7dbd0fa2dbe80aa (diff) | |
| download | coreboot-3a96074441c4e2b28d6d6961b94fec5c4eada8ec.tar.gz coreboot-3a96074441c4e2b28d6d6961b94fec5c4eada8ec.tar.bz2 coreboot-3a96074441c4e2b28d6d6961b94fec5c4eada8ec.zip | |
src/arch/ppc64/*: pass FDT address to payload
It's available in %r3 in bootblock and needs to be passed to payload in
%r27. We use one of two hypervisor's special registers as a buffer,
which aren't used for anything by the code.
Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/ppc64/bootblock_crt0.S | 6 | ||||
| -rw-r--r-- | src/include/cpu/power/spr.h | 3 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-power9/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-power9/ramstage.c | 21 |
4 files changed, 32 insertions, 0 deletions
diff --git a/src/arch/ppc64/bootblock_crt0.S b/src/arch/ppc64/bootblock_crt0.S index 3988583bee3e..5a9496024e2a 100644 --- a/src/arch/ppc64/bootblock_crt0.S +++ b/src/arch/ppc64/bootblock_crt0.S @@ -3,6 +3,8 @@ * Early initialization code for POWER8/POWER9. */ +#include <cpu/power/spr.h> + #define FIXUP_ENDIAN \ tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ b $+44; /* Skip trampoline if endian is good */ \ @@ -35,6 +37,10 @@ _start: nop FIXUP_ENDIAN + /* Store FDT address provided by QEMU in %r3 to pass it later to + * payload */ + mtspr SPR_HSPRG0, %r3 + /* Set program priority to medium */ or %r2, %r2, %r2 diff --git a/src/include/cpu/power/spr.h b/src/include/cpu/power/spr.h index f22a6cab3df7..3b229f73a33a 100644 --- a/src/include/cpu/power/spr.h +++ b/src/include/cpu/power/spr.h @@ -9,6 +9,9 @@ #define SPR_PVR_REV_MASK (PPC_BITMASK(52, 55) | PPC_BITMASK(60, 63)) #define SPR_PVR_REV(maj, min) (PPC_SHIFT((maj), 55) | PPC_SHIFT((min), 63)) +#define SPR_HSPRG0 0x130 +#define SPR_HSPRG1 0x131 + #define SPR_HRMOR 0x139 #define SPR_HMER 0x150 diff --git a/src/mainboard/emulation/qemu-power9/Makefile.inc b/src/mainboard/emulation/qemu-power9/Makefile.inc index bd905a302982..ace00a75b78e 100644 --- a/src/mainboard/emulation/qemu-power9/Makefile.inc +++ b/src/mainboard/emulation/qemu-power9/Makefile.inc @@ -2,3 +2,5 @@ romstage-y += cbmem.c romstage-y += romstage.c + +ramstage-y += ramstage.c diff --git a/src/mainboard/emulation/qemu-power9/ramstage.c b/src/mainboard/emulation/qemu-power9/ramstage.c new file mode 100644 index 000000000000..c92587b69622 --- /dev/null +++ b/src/mainboard/emulation/qemu-power9/ramstage.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/power/spr.h> +#include <program_loading.h> + +/* + * Payload's entry point is an offset to the real entry point, not to OPD + * (Official Procedure Descriptor) for entry point. + * + * Also pass FDT address to payload stored in SPR_HSPRG0 by bootblock. + */ +void platform_prog_run(struct prog *prog) +{ + asm volatile( + "mfspr %%r27, %0\n" /* pass pointer to FDT */ + "mtctr %2\n" + "mr 3, %1\n" + "bctr\n" + :: "i"(SPR_HSPRG0), "r"(prog_entry_arg(prog)), "r"(prog_entry(prog)) + : "memory"); +} |