mb/asus/p8x7x-series: Add P8C WS as a variant of P8X7X series

Mainboard information can be found in the included documentation.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Idb696193e5a67c42adf45e54d455d2dff7681ca7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

13 files changed, 518 insertions, 0 deletions

diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig
index 4f4f31b3f013..bc246e7d8d65 100644
--- a/src/mainboard/asus/p8x7x-series/Kconfig
+++ b/src/mainboard/asus/p8x7x-series/Kconfig
@@ -21,6 +21,7 @@ config MAINBOARD_DIR
 
 config VARIANT_DIR
 	string
+	default "p8c_ws"      if BOARD_ASUS_P8C_WS
 	default "p8h77-v"     if BOARD_ASUS_P8H77_V
 	default "p8z77-m_pro" if BOARD_ASUS_P8Z77_M_PRO
 	default "p8z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2
@@ -28,6 +29,7 @@ config VARIANT_DIR
 
 config MAINBOARD_PART_NUMBER
 	string
+	default "P8C WS"      if BOARD_ASUS_P8C_WS
 	default "P8H77-V"     if BOARD_ASUS_P8H77_V
 	default "P8Z77-M PRO" if BOARD_ASUS_P8Z77_M_PRO
 	default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2
diff --git a/src/mainboard/asus/p8x7x-series/Kconfig.name b/src/mainboard/asus/p8x7x-series/Kconfig.name
index 3509eead023a..b4d89481c297 100644
--- a/src/mainboard/asus/p8x7x-series/Kconfig.name
+++ b/src/mainboard/asus/p8x7x-series/Kconfig.name
@@ -1,3 +1,11 @@
+config BOARD_ASUS_P8C_WS
+	bool "P8C_WS"
+	select BOARD_ASUS_P8X7X_SERIES
+	select BOARD_ROMSIZE_KB_8192
+	select MAINBOARD_HAS_LPC_TPM
+	select SUPERIO_NUVOTON_NCT6776
+	select USE_NATIVE_RAMINIT
+
 config BOARD_ASUS_P8H77_V
 	bool "P8H77-V"
 	select BOARD_ASUS_P8X7X_SERIES
diff --git a/src/mainboard/asus/p8x7x-series/dsdt.asl b/src/mainboard/asus/p8x7x-series/dsdt.asl
index e8e2b3a3e560..e93fe97c530d 100644
--- a/src/mainboard/asus/p8x7x-series/dsdt.asl
+++ b/src/mainboard/asus/p8x7x-series/dsdt.asl
@@ -22,5 +22,8 @@ DefinitionBlock(
 	{
 		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
 		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+		#if CONFIG(BOARD_ASUS_P8C_WS)
+		#include "variants/p8c_ws/pci.asl"
+		#endif
 	}
 }
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/board_info.txt b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/board_info.txt
new file mode 100644
index 000000000000..44dcf5b0ba24
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/supportonly/p8c_ws/helpdesk_knowledge/
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
+Release year: 2013
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.default
new file mode 100644
index 000000000000..c7aa6208f41e
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.default
@@ -0,0 +1,6 @@
+boot_option=Fallback
+debug_level=Debug
+nmi=Disable
+power_on_after_fail=Disable
+sata_mode=AHCI
+gfx_uma_size=64M
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.layout
new file mode 100644
index 000000000000..0f9de5ed1864
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/cmos.layout
@@ -0,0 +1,86 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	2	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	3	debug_level
+
+# coreboot config options: southbridge
+408	1	e	1	nmi
+
+409	2	e	4	power_on_after_fail
+411	2	e	5	sata_mode
+
+# coreboot config options: northbridge
+416	5	e	6	gfx_uma_size
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+#ID	value	text
+
+# Generic on/off enum
+1	0	Disable
+1	1	Enable
+
+# boot_option
+2	0	Fallback
+2	1	Normal
+
+# debug_level
+3	0	Emergency
+3	1	Alert
+3	2	Critical
+3	3	Error
+3	4	Warning
+3	5	Notice
+3	6	Info
+3	7	Debug
+3	8	Spew
+
+# power_on_after_fail
+4	0	Disable
+4	1	Enable
+4	2	Keep
+
+# sata_mode
+5	0	AHCI
+5	1	Compatible
+5	2	Legacy
+
+# gfx_uma_size (Intel IGP Video RAM size)
+6	0	32M
+6	1	64M
+6	2	96M
+6	3	128M
+6	4	160M
+6	5	192M
+6	6	224M
+6	7	256M
+6	8	288M
+6	9	320M
+6	10	352M
+6	11	384M
+6	12	416M
+6	13	448M
+6	14	480M
+6	15	512M
+6	16	1024M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 423 984
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/data.vbt b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/data.vbt
new file mode 100644
index 000000000000..fce6b676453c
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/data.vbt
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c
new file mode 100644
index 000000000000..9f84b49e6b19
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6776/nct6776.h>
+
+#define GLOBAL_DEV PNP_DEV(0x2e, 0)
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
+#define ACPI_DEV   PNP_DEV(0x2e, NCT6776_ACPI)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 0, 0 },
+	{ 1, 0, 0 },
+	{ 1, 0, 1 },
+	{ 1, 0, 1 },
+	{ 1, 0, 2 },
+	{ 1, 0, 2 },
+	{ 1, 0, 3 },
+	{ 1, 0, 3 },
+	{ 1, 0, 4 },
+	{ 1, 0, 4 },
+	{ 1, 0, 6 },
+	{ 1, 0, 5 },
+	{ 1, 0, 5 },
+	{ 1, 0, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+	nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
+
+	/* Select SIO pin states */
+	pnp_write_config(GLOBAL_DEV, 0x1a, 0xc8);
+	pnp_write_config(GLOBAL_DEV, 0x1b, 0x0e);
+	pnp_write_config(GLOBAL_DEV, 0x1c, 0x83);
+	pnp_write_config(GLOBAL_DEV, 0x24, 0x20);
+	pnp_write_config(GLOBAL_DEV, 0x27, 0x10);
+	pnp_write_config(GLOBAL_DEV, 0x2a, 0x68);
+	pnp_write_config(GLOBAL_DEV, 0x2c, 0x00);
+
+	/* Power RAM in S3 */
+	pnp_set_logical_device(ACPI_DEV);
+	pnp_write_config(ACPI_DEV, 0xe4, 0x10);
+
+	pnp_set_logical_device(SERIAL_DEV);
+
+	nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+
+	/* Enable UART */
+	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[1], 0x51, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+	read_spd(&spd[3], 0x53, id_only);
+}
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/gma-mainboard.ads b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/gma-mainboard.ads
new file mode 100644
index 000000000000..c9e432692416
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/gma-mainboard.ads
@@ -0,0 +1,16 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (HDMI1,
+      Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/gpio.c b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/gpio.c
new file mode 100644
index 000000000000..a93ad6aa1a4e
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/gpio.c
@@ -0,0 +1,183 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_NATIVE,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_NATIVE,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_NATIVE,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio12 = GPIO_LEVEL_LOW,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+	.gpio31 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio6 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_NATIVE,
+	.gpio36 = GPIO_MODE_NATIVE,
+	.gpio37 = GPIO_MODE_NATIVE,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_NATIVE,
+	.gpio52 = GPIO_MODE_NATIVE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_NATIVE,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_OUTPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+	.gpio33 = GPIO_LEVEL_HIGH,
+	.gpio48 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_NATIVE,
+	.gpio71 = GPIO_MODE_NATIVE,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio72 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/hda_verb.c
new file mode 100644
index 000000000000..574da72fe006
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/hda_verb.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0892,	/* Codec Vendor / Device ID: Realtek ALC892 */
+	0x104384fb,	/* Subsystem ID */
+	15,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x104384fb),
+	AZALIA_PIN_CFG(0, 0x11, 0x99430140),
+	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, 0x01011012),
+	AZALIA_PIN_CFG(0, 0x16, 0x01016011),
+	AZALIA_PIN_CFG(0, 0x17, 0x01012014),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19850),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181305f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
+	AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4005e601),
+	AZALIA_PIN_CFG(0, 0x1e, 0x014b6130),
+	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb
new file mode 100644
index 000000000000..4de539b1e233
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb
@@ -0,0 +1,87 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		device pci 01.1 on  end		# PCIEX16_2 (electrical x8)
+		device pci 06.0 on  end		# PCIEX16_3 (electrical x4)
+		subsystemid 0x1043 0x84ca inherit
+		chip southbridge/intel/bd82x6x
+			register "gen1_dec" = "0x000c0291"
+			device pci 1c.0 on  end		# RP #1: PCIEX16_4 (electrical x4)
+			device pci 1c.1 off end		# RP #2:
+			device pci 1c.2 off end		# RP #3:
+			device pci 1c.3 off end		# RP #4:
+			device pci 1c.4 on  end		# RP #5: PCIEX1_1
+			device pci 1c.5 on  end		# RP #6: 82574 GbE #1
+			device pci 1c.6 on  end		# RP #7: 82574 GbE #2
+			device pci 1c.7 off end		# RP #8:
+			device pci 1e.0 on  end		# PCI bridge
+			device pci 1f.0 on		# LPC bridge
+				chip superio/nuvoton/nct6776
+					device pnp 2e.0   off end # Floppy
+					device pnp 2e.1   on      # Parallel
+						io  0x60 = 0x0378
+						irq 0x70 = 5
+						drq 0x74 = 4      # No DMA
+						irq 0xf0 = 0x3c   # Printer mode
+					end
+					device pnp 2e.2   on      # UART A
+						io  0x60 = 0x03f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3   off end # UART B, IR
+					device pnp 2e.5   on      # PS/2 KBC
+						io  0x60 = 0x0060
+						io  0x62 = 0x0064
+						irq 0x70 = 1      # Keyboard
+						irq 0x72 = 12     # Mouse
+					end
+					device pnp 2e.6   off end # CIR
+					device pnp 2e.7   off end # GPIO8
+					device pnp 2e.107 off end # GPIO9
+					device pnp 2e.8   off end # WDT
+					device pnp 2e.108 off end # GPIO0
+					device pnp 2e.208 off end # GPIOA
+					device pnp 2e.308 off end # GPIO base
+					device pnp 2e.109 off 	  # GPIO1
+						irq 0xf0 = 0xfb
+						irq 0xf1 = 0x0
+						irq 0xf5 = 0xff
+						irq 0xf7 = 0xff
+					end
+					device pnp 2e.209 on      # GPIO2
+						irq 0xe0 = 0xef
+					end
+					device pnp 2e.309 on      # GPIO3
+						irq 0xea = 0xff
+					end
+					device pnp 2e.409 on  end # GPIO4
+					device pnp 2e.509 on  end # GPIO5
+					device pnp 2e.609 on  end # GPIO6
+					device pnp 2e.709 off end # GPIO7
+					device pnp 2e.a   on      # ACPI
+						irq 0xe6 = 0x0c
+						irq 0xe7 = 0x11
+						irq 0xf2 = 0x5d
+					end
+					device pnp 2e.b   on      # HWM, LED
+						io  0x60 = 0x0290
+						io  0x62 = 0x0000
+					end
+					device pnp 2e.d   off end # VID
+					device pnp 2e.e   off end # CIR wake-up
+					device pnp 2e.f   off     # GPIO PP/OD
+						# Enable i2c slave to 0x1d
+						irq 0xf0 = 0x9d
+					end
+					device pnp 2e.14  off end # SVID
+					device pnp 2e.16  off end # Deep sleep
+					device pnp 2e.17  off end # GPIOA
+				end
+				chip drivers/pc80/tpm
+					device pnp c31.0 on end	# TPM
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/pci.asl b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/pci.asl
new file mode 100644
index 000000000000..76af84ca0410
--- /dev/null
+++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/pci.asl
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Intel PCI to PCI bridge 0:1e.0
+
+Device (PCIB)
+{
+	Name (_ADR, 0x001E0000)  // _ADR: Address
+	Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
+
+	Method (_PRT)  // _PRT: PCI Interrupt Routing Table
+	{
+		If (PICM) {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, 0, 0x10 },
+				Package() { 0x0000ffff, 1, 0, 0x11 },
+				Package() { 0x0000ffff, 2, 0, 0x12 },
+				Package() { 0x0000ffff, 3, 0, 0x13 },
+				Package() { 0x0003ffff, 0, 0, 0x13 },
+			})
+		}
+		Return (Package() {
+			Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+		})
+	}
+}