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| author | Fred Reitberger <reitbergerfred@gmail.com> | 2022-10-18 14:51:04 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-21 21:42:00 +0000 |
| commit | 460ea9d5d250714c94cb9e83eb585e02f04e3000 (patch) | |
| tree | 7ec9373332ff4ca1c9055ee7337b1722050d9bab /src | |
| parent | 1cffc55d35ee421f126d5491f2a60943dc6c6255 (diff) | |
| download | coreboot-460ea9d5d250714c94cb9e83eb585e02f04e3000.tar.gz coreboot-460ea9d5d250714c94cb9e83eb585e02f04e3000.tar.bz2 coreboot-460ea9d5d250714c94cb9e83eb585e02f04e3000.zip | |
soc/amd/*/smi.h: Use BIT() for clarity
Use the BIT() macro for single-bit constants.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I490f0093d55813260fcdb7303a94accfa90e75e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/smi.h | 20 | ||||
| -rw-r--r-- | src/soc/amd/mendocino/include/soc/smi.h | 20 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/smi.h | 20 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/smi.h | 20 |
4 files changed, 41 insertions, 39 deletions
diff --git a/src/soc/amd/cezanne/include/soc/smi.h b/src/soc/amd/cezanne/include/soc/smi.h index aad412308377..5fc256b6eccc 100644 --- a/src/soc/amd/cezanne/include/soc/smi.h +++ b/src/soc/amd/cezanne/include/soc/smi.h @@ -149,22 +149,22 @@ #define SMI_REG_SMISTS4 0x90 #define SMI_REG_POINTER 0x94 -# define SMI_STATUS_SRC_SCI (1 << 0) -# define SMI_STATUS_SRC_0 (1 << 1) /* SMIx80 */ -# define SMI_STATUS_SRC_1 (1 << 2) /* SMIx84... */ -# define SMI_STATUS_SRC_2 (1 << 3) -# define SMI_STATUS_SRC_3 (1 << 4) -# define SMI_STATUS_SRC_4 (1 << 5) +# define SMI_STATUS_SRC_SCI BIT(0) +# define SMI_STATUS_SRC_0 BIT(1) /* SMIx80 */ +# define SMI_STATUS_SRC_1 BIT(2) /* SMIx84... */ +# define SMI_STATUS_SRC_2 BIT(3) +# define SMI_STATUS_SRC_3 BIT(4) +# define SMI_STATUS_SRC_4 BIT(5) #define SMI_TIMER 0x96 #define SMI_TIMER_MASK 0x7fff #define SMI_TIMER_EN (1 << 15) #define SMI_REG_SMITRIG0 0x98 -# define SMITRIG0_PSP (1 << 25) -# define SMITRG0_EOS (1 << 28) -# define SMI_TIMER_SEL (1 << 29) -# define SMITRG0_SMIENB (1 << 31) +# define SMITRIG0_PSP BIT(25) +# define SMITRG0_EOS BIT(28) +# define SMI_TIMER_SEL BIT(29) +# define SMITRG0_SMIENB BIT(31) #define SMI_REG_CONTROL0 0xa0 #define SMI_REG_CONTROL1 0xa4 diff --git a/src/soc/amd/mendocino/include/soc/smi.h b/src/soc/amd/mendocino/include/soc/smi.h index 1525e3419974..4a4ec2483c7d 100644 --- a/src/soc/amd/mendocino/include/soc/smi.h +++ b/src/soc/amd/mendocino/include/soc/smi.h @@ -156,22 +156,22 @@ #define SMI_REG_SMISTS4 0x90 #define SMI_REG_POINTER 0x94 -# define SMI_STATUS_SRC_SCI (1 << 0) -# define SMI_STATUS_SRC_0 (1 << 1) /* SMIx80 */ -# define SMI_STATUS_SRC_1 (1 << 2) /* SMIx84... */ -# define SMI_STATUS_SRC_2 (1 << 3) -# define SMI_STATUS_SRC_3 (1 << 4) -# define SMI_STATUS_SRC_4 (1 << 5) +# define SMI_STATUS_SRC_SCI BIT(0) +# define SMI_STATUS_SRC_0 BIT(1) /* SMIx80 */ +# define SMI_STATUS_SRC_1 BIT(2) /* SMIx84... */ +# define SMI_STATUS_SRC_2 BIT(3) +# define SMI_STATUS_SRC_3 BIT(4) +# define SMI_STATUS_SRC_4 BIT(5) #define SMI_TIMER 0x96 #define SMI_TIMER_MASK 0x7fff #define SMI_TIMER_EN (1 << 15) #define SMI_REG_SMITRIG0 0x98 -# define SMITRIG0_PSP (1 << 25) -# define SMITRG0_EOS (1 << 28) -# define SMI_TIMER_SEL (1 << 29) -# define SMITRG0_SMIENB (1 << 31) +# define SMITRIG0_PSP BIT(25) +# define SMITRG0_EOS BIT(28) +# define SMI_TIMER_SEL BIT(29) +# define SMITRG0_SMIENB BIT(31) #define SMI_REG_CONTROL0 0xa0 #define SMI_REG_CONTROL1 0xa4 diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index dba3bea63e64..265c10c13a06 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -151,22 +151,22 @@ #define SMI_REG_SMISTS4 0x90 #define SMI_REG_POINTER 0x94 -# define SMI_STATUS_SRC_SCI (1 << 0) -# define SMI_STATUS_SRC_0 (1 << 1) /* SMIx80 */ -# define SMI_STATUS_SRC_1 (1 << 2) /* SMIx84... */ -# define SMI_STATUS_SRC_2 (1 << 3) -# define SMI_STATUS_SRC_3 (1 << 4) -# define SMI_STATUS_SRC_4 (1 << 5) +# define SMI_STATUS_SRC_SCI BIT(0) +# define SMI_STATUS_SRC_0 BIT(1) /* SMIx80 */ +# define SMI_STATUS_SRC_1 BIT(2) /* SMIx84... */ +# define SMI_STATUS_SRC_2 BIT(3) +# define SMI_STATUS_SRC_3 BIT(4) +# define SMI_STATUS_SRC_4 BIT(5) #define SMI_TIMER 0x96 #define SMI_TIMER_MASK 0x7fff #define SMI_TIMER_EN (1 << 15) #define SMI_REG_SMITRIG0 0x98 -# define SMITRIG0_PSP (1 << 25) -# define SMITRG0_EOS (1 << 28) -# define SMI_TIMER_SEL (1 << 29) -# define SMITRG0_SMIENB (1 << 31) +# define SMITRIG0_PSP BIT(25) +# define SMITRG0_EOS BIT(28) +# define SMI_TIMER_SEL BIT(29) +# define SMITRG0_SMIENB BIT(31) #define SMI_REG_CONTROL0 0xa0 #define SMI_REG_CONTROL1 0xa4 diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 3ce41df40c7a..ccdd3c5581fc 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -3,6 +3,8 @@ #ifndef AMD_STONEYRIDGE_SMI_H #define AMD_STONEYRIDGE_SMI_H +#include <types.h> + #define SMI_GEVENTS 24 #define SCIMAPS 59 /* 0..58 */ #define SCI_GPES 32 @@ -149,21 +151,21 @@ #define SMI_REG_SMISTS4 0x90 #define SMI_REG_POINTER 0x94 -# define SMI_STATUS_SRC_SCI (1 << 0) -# define SMI_STATUS_SRC_0 (1 << 1) /* SMIx80 */ -# define SMI_STATUS_SRC_1 (1 << 2) /* SMIx84... */ -# define SMI_STATUS_SRC_2 (1 << 3) -# define SMI_STATUS_SRC_3 (1 << 4) -# define SMI_STATUS_SRC_4 (1 << 5) +# define SMI_STATUS_SRC_SCI BIT(0) +# define SMI_STATUS_SRC_0 BIT(1) /* SMIx80 */ +# define SMI_STATUS_SRC_1 BIT(2) /* SMIx84... */ +# define SMI_STATUS_SRC_2 BIT(3) +# define SMI_STATUS_SRC_3 BIT(4) +# define SMI_STATUS_SRC_4 BIT(5) #define SMI_TIMER 0x96 #define SMI_TIMER_MASK 0x7fff #define SMI_TIMER_EN (1 << 15) #define SMI_REG_SMITRIG0 0x98 -# define SMITRG0_EOS (1 << 28) -# define SMI_TIMER_SEL (1 << 29) -# define SMITRG0_SMIENB (1 << 31) +# define SMITRG0_EOS BIT(28) +# define SMI_TIMER_SEL BIT(29) +# define SMITRG0_SMIENB BIT(31) #define SMI_REG_CONTROL0 0xa0 #define SMI_REG_CONTROL1 0xa4 |