diff options
| author | Harsha B R <harsha.b.r@intel.com> | 2022-12-21 11:08:46 +0530 |
|---|---|---|
| committer | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2023-01-11 06:19:54 +0000 |
| commit | 4954a0f611475f3deea768f700f9f4b59bfc5304 (patch) | |
| tree | 5ab478d32ab2e29d420b004f30b6de967d50d31d /src | |
| parent | 8b32e404e1b308125cf35e164669b0f89e141934 (diff) | |
| download | coreboot-4954a0f611475f3deea768f700f9f4b59bfc5304.tar.gz coreboot-4954a0f611475f3deea768f700f9f4b59bfc5304.tar.bz2 coreboot-4954a0f611475f3deea768f700f9f4b59bfc5304.zip | |
mb/intel/mtlrvp: Configure USB devices for MTL-RVP
This patch adds OC configuration of USB devices for MTL-RVP
as per MTL-RVP design specification,
USB 2.0
usb2_ports0 -> OC0
usb2_ports1 -> OC0
usb2_ports2 -> OC0
usb2_ports3 -> OC0
usb2_ports4 -> OC0
usb2_ports5 -> OC0
usb2_ports6 -> OC_SKIP
usb2_ports7 -> OC_SKIP
usb2_ports8 -> OC_SKIP
usb2_ports9 -> OC_SKIP
USB 3.2 Gen 2x1
usb3_ports0 -> OC0
usb3_ports1 -> OC0
TCPx
tcss_ports0 -> OC0
tcss_ports1 -> OC0
tcss_ports2 -> OC0
tcss_ports3 -> OC0
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp to chromeOS
(on top of CB: 66190).
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: If1a0c31b7bf0f3fc06f039ad76b0cdd41f7cdd90
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index d28b7b197025..8cdbeea5a843 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -17,6 +17,25 @@ chip soc/intel/meteorlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C1 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C2 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C3 + register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0 + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN / MCF + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # MCF / M.2 WWAN + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2_Type-A1 / M.2 WWAN + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2_Type-A0 / USB Flex Connector + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)" + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)" + register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC0)" + device domain 0 on device ref igpu on end device ref heci1 on end |