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| author | Tongtong Pan <pantongtong@huaqin.corp-partner.google.com> | 2025-04-08 20:51:10 +0800 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@gmail.com> | 2025-04-15 13:20:18 +0000 |
| commit | 49a257a7db8fb6245bc63d0bd06f56a16c4789e4 (patch) | |
| tree | 41128d793314e73c5b95e5fba9c2cebfc895af7b /src | |
| parent | 3ea8f422550ff8672f1b08f81c1bd3791a3096d2 (diff) | |
| download | coreboot-49a257a7db8fb6245bc63d0bd06f56a16c4789e4.tar.gz coreboot-49a257a7db8fb6245bc63d0bd06f56a16c4789e4.tar.bz2 coreboot-49a257a7db8fb6245bc63d0bd06f56a16c4789e4.zip | |
mb/google/fatcat/var/felino: Use GPP_E03 for EC_SYNC_IRQ
Use GPP_E03 as the EC sync interrupt and provide this value
to the embedded controller to be exported to the OS.
BUG=b:403383143
Test=emerge-fatcat coreboot and Confirm the log:
cros_ec_lpcs GOOG0004:00: Chrome EC device registered
Change-Id: If7d120fcf2de8dbbbc399d2ead4e294d11ea8a14
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87210
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h | 2 | ||||
| -rw-r--r-- | src/mainboard/google/fatcat/variants/felino/gpio.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h index dc4ce131856d..067c36116156 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h @@ -26,7 +26,7 @@ /* Used to gate SoC's SLP_S0# signal */ #define GPIO_SLP_S0_GATE GPP_F23 #elif CONFIG(BOARD_GOOGLE_FELINO) - #define EC_SYNC_IRQ 0 /* TODO */ + #define EC_SYNC_IRQ GPP_E03_IRQ #define GPIO_PCH_WP 0 /* TODO */ /* Used to gate SoC's SLP_S0# signal */ #define GPIO_SLP_S0_GATE GPP_D03 diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c index a70e9fe09fca..a7df5fccb7d1 100644 --- a/src/mainboard/google/fatcat/variants/felino/gpio.c +++ b/src/mainboard/google/fatcat/variants/felino/gpio.c @@ -206,8 +206,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPP_E01, NONE, PLTRST), /* GPP_E02: NC */ PAD_NC(GPP_E02, NONE), - /* GPP_E03: NC */ - PAD_NC(GPP_E03, NONE), + /* GPP_E03: EC_SYNC_IRQ */ + PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT), /* GPP_E05: NC */ PAD_NC(GPP_E05, NONE), /* GPP_E06: GPP_E06 */ |