cpu/x86: Declare SMM_ASEG

This is really an inverse of SMM_TSEG to flag
platforms that should potentially move away
from ASEG implementation.

Change-Id: I3b9007c55c75a59a9e6acc0a0e701300f7d21f87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

9 files changed, 20 insertions, 9 deletions

diff --git a/src/Kconfig b/src/Kconfig
index 778f1694b6a2..38209ee6e1dc 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -543,10 +543,6 @@ config HAVE_OPTION_TABLE
 	  file containing NVRAM/CMOS bit definitions.
 	  It defaults to 'n' but can be selected in mainboard/*/Kconfig.
 
-config HAVE_SMI_HANDLER
-	bool
-	default n
-
 config PCI_IO_CFG_EXT
 	bool
 	default n
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 5f7e0f998763..4c5463cc8a20 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -30,6 +30,7 @@ config CPU_AMD_AGESA
 	select LAPIC_MONOTONIC_TIMER
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select POSTCAR_STAGE
+	select SMM_ASEG
 
 if CPU_AMD_AGESA
 
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
index 8dc7f5abf9e1..a902089099e9 100644
--- a/src/cpu/amd/pi/Kconfig
+++ b/src/cpu/amd/pi/Kconfig
@@ -29,6 +29,7 @@ config CPU_AMD_PI
 	select LAPIC_MONOTONIC_TIMER
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select POSTCAR_STAGE if !BINARYPI_LEGACY_WRAPPER
+	select SMM_ASEG
 
 if CPU_AMD_PI
 
diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig
index 5ef1539995eb..9e707756509c 100644
--- a/src/cpu/intel/model_f2x/Kconfig
+++ b/src/cpu/intel/model_f2x/Kconfig
@@ -6,3 +6,4 @@ config CPU_INTEL_MODEL_F2X
 	select ARCH_RAMSTAGE_X86_32
 	select SMP
 	select SUPPORT_CPU_UCODE_IN_CBFS
+	select SMM_ASEG
diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
index 70cce9b705b8..0473e2f7f072 100644
--- a/src/cpu/qemu-x86/Kconfig
+++ b/src/cpu/qemu-x86/Kconfig
@@ -22,3 +22,4 @@ config CPU_QEMU_X86
 	select SMP
 	select UDELAY_TSC
 	select C_ENVIRONMENT_BOOTBLOCK
+	select SMM_ASEG
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 99a70750af71..d230a57e3f14 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -88,6 +88,15 @@ config LOGICAL_CPUS
 	bool
 	default y
 
+config HAVE_SMI_HANDLER
+	bool
+	default n
+	depends on (SMM_ASEG || SMM_TSEG)
+
+config SMM_ASEG
+	bool
+	default n
+
 config SMM_TSEG
 	bool
 	default n
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index c282904de9ea..e23b082aa7ab 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -32,10 +32,9 @@
 // ADDR32() macro
 #include <arch/registers.h>
 
-#if CONFIG(SMM_TSEG)
-#error "Don't use this file with TSEG."
-
-#endif /* CONFIG_SMM_TSEG */
+#if !CONFIG(SMM_ASEG)
+#error "Only use this file with ASEG."
+#endif /* CONFIG_SMM_ASEG */
 
 #define LAPIC_ID 0xfee00020
 
diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc
index ae0a10f96fec..a8931fffc1bc 100644
--- a/src/southbridge/intel/i82801dx/Makefile.inc
+++ b/src/southbridge/intel/i82801dx/Makefile.inc
@@ -24,8 +24,11 @@ ramstage-y += lpc.c
 ramstage-y += usb.c
 ramstage-y += usb2.c
 
+ifeq ($(CONFIG_SMM_ASEG),y)
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S
+endif
+
 smm-y += smihandler.c
 
 romstage-y += early_smbus.c
diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc
index 0b9ade824eb5..49db1230b75e 100644
--- a/src/southbridge/intel/i82801ix/Makefile.inc
+++ b/src/southbridge/intel/i82801ix/Makefile.inc
@@ -29,7 +29,7 @@ ramstage-y += ../common/pciehp.c
 
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
-ifneq ($(CONFIG_SMM_TSEG),y)
+ifeq ($(CONFIG_SMM_ASEG),y)
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S
 endif