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| author | Subrata Banik <subratabanik@google.com> | 2022-10-11 17:27:14 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-14 16:04:15 +0000 |
| commit | 4e85ec705e08c37a6e071bbb9d5f381eea018283 (patch) | |
| tree | 98b0e0c8f1bc56caed3848ce0b224b68a165ede8 /src | |
| parent | 9fb58575d66ef72a4f0985f542c562693a9526d2 (diff) | |
| download | coreboot-4e85ec705e08c37a6e071bbb9d5f381eea018283.tar.gz coreboot-4e85ec705e08c37a6e071bbb9d5f381eea018283.tar.bz2 coreboot-4e85ec705e08c37a6e071bbb9d5f381eea018283.zip | |
soc/intel/alderlake: Create helper header file for UFS
This patch creates helper header file (ufs.h) for UFS to keep
required registers details and ACPI device id for UFS.
BUG=none
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If08c54eb706876a4255542a708aa5fcd8bf43c55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68299
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/ufs.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/ufs.h b/src/soc/intel/alderlake/include/soc/ufs.h new file mode 100644 index 000000000000..3b5e33d0fb03 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/ufs.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on Intel Alder Lake Processor PCH Datasheet + * Document number: 645550 + */ + +#ifndef _SOC_ALDERLAKE_UFS_H_ +#define _SOC_ALDERLAKE_UFS_H_ + +#include <soc/pci_devs.h> + +/* Calculate _ADR for Intel UFS Controller */ +#define UFS_ACPI_DEVICE (PCH_DEV_SLOT_ISH << 16 | 0x0007) + +#define R_SCS_CFG_PCS 0x84 +#define R_SCS_CFG_PG_CONFIG 0xA2 + +#define R_SCS_PCR_1C20 0x1C20 +#define R_SCS_PCR_4820 0x4820 +#define R_SCS_PCR_4020 0x4020 +#define R_SCS_PCR_5820 0x5820 +#define R_SCS_PCR_5C20 0x5C20 +#define R_SCS_PCR_1078 0x1078 +#define R_PMC_PWRM_LTR_IGN 0x1B0C + +#endif |