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| author | Jeremy Soller <jackpot51@gmail.com> | 2022-05-26 09:02:13 -0600 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-07-28 19:59:44 +0000 |
| commit | 5219ee160eb79f383321c062da388f65718c9946 (patch) | |
| tree | 0f5611cc3e278fe830f79ed8695422f58e8f51be /src | |
| parent | dca8583f17a2b26269a51da929c0892cce19b532 (diff) | |
| download | coreboot-5219ee160eb79f383321c062da388f65718c9946.tar.gz coreboot-5219ee160eb79f383321c062da388f65718c9946.tar.bz2 coreboot-5219ee160eb79f383321c062da388f65718c9946.zip | |
soc/intel/alderlake: Enable LPIT support
Add SLP_S0 residency register and enable LPIT support.
Change-Id: I45e1fc9df3e782cdaac810af3189c5797b1fe413
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/pmc.h | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index adb6a4355ffa..af1a04934c76 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -83,6 +83,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ select SOC_INTEL_COMMON_BLOCK_CAR diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h index 8600d0e07824..81a99e00ecaa 100644 --- a/src/soc/intel/alderlake/include/soc/pmc.h +++ b/src/soc/intel/alderlake/include/soc/pmc.h @@ -153,6 +153,8 @@ extern struct device_operations pmc_ops; #define HPR_CAUSE0_MI_HRPC (1 << 9) #define HPR_CAUSE0_MI_HR (1 << 8) +#define SLP_S0_RES 0x193c + #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) |