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| author | Martin Roth <gaumless@gmail.com> | 2022-10-17 16:19:45 -0600 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-10-28 21:37:24 +0000 |
| commit | 530b111c42e5d87d95f84d92228817186b655500 (patch) | |
| tree | a3d79a3a474bac4d070e63122a61165215753141 /src | |
| parent | 300338fccfaf046be4ba728fd1b5431fd1057faa (diff) | |
| download | coreboot-530b111c42e5d87d95f84d92228817186b655500.tar.gz coreboot-530b111c42e5d87d95f84d92228817186b655500.tar.bz2 coreboot-530b111c42e5d87d95f84d92228817186b655500.zip | |
soc/amd/common: Add coreboot post codes to STB
Adding coreboot's postcodes to the smart trace buffer lets us see the
entire boot flow in one place.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8eb9f777b303622c144203eb53e2e1bf3314afaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/stb.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/stb/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/amd/common/block/stb/stb.c | 6 |
3 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/stb.h b/src/soc/amd/common/block/include/amdblocks/stb.h index 51b01948f8c8..c8851f89a33b 100644 --- a/src/soc/amd/common/block/include/amdblocks/stb.h +++ b/src/soc/amd/common/block/include/amdblocks/stb.h @@ -7,6 +7,7 @@ #define AMD_STB_PMI_0 0x30600 +#define AMD_STB_COREBOOT_POST_PREFIX 0xBA000000 #define AMD_STB_COREBOOT_MARKER 0xBAADF00D struct stb_entry_struct { diff --git a/src/soc/amd/common/block/stb/Kconfig b/src/soc/amd/common/block/stb/Kconfig index 8935e92556a6..fe2b5b7a1a37 100644 --- a/src/soc/amd/common/block/stb/Kconfig +++ b/src/soc/amd/common/block/stb/Kconfig @@ -14,4 +14,10 @@ config WRITE_STB_BUFFER_TO_CONSOLE points through the boot process. Note that this will prevent the entries from being stored if the Spill-to-DRAM feature is enabled. +config ADD_POSTCODES_TO_STB + bool "Add coreboot postcodes to STB" + default y + help + Add coreboot's postcodes to the smart trace buffer + endif diff --git a/src/soc/amd/common/block/stb/stb.c b/src/soc/amd/common/block/stb/stb.c index 074a4ed7148b..0cea5c3d6758 100644 --- a/src/soc/amd/common/block/stb/stb.c +++ b/src/soc/amd/common/block/stb/stb.c @@ -18,6 +18,12 @@ static uint32_t stb_read32(uint32_t reg) return smn_read32(STB_CFG_SMN_ADDR + reg); } +void soc_post_code(uint8_t value) +{ + if (CONFIG(ADD_POSTCODES_TO_STB)) + stb_write32(AMD_STB_PMI_0, AMD_STB_COREBOOT_POST_PREFIX | value); +} + void write_stb_to_console(void) { int i; |