diff options
author | Ronald Hoogenboom <hoogenboom30@zonnet.nl> | 2008-02-25 19:36:20 +0000 |
---|---|---|
committer | Ward Vandewege <ward@gnu.org> | 2008-02-25 19:36:20 +0000 |
commit | 56cf01f29d7549f11cdd329d5ca8a2e163665f3a (patch) | |
tree | 1067560c9e7740ac9bfa941211d07657aa2f972a /src | |
parent | 8684520b94a87cb20de1b9c41dfa902f71cb00d4 (diff) | |
download | coreboot-56cf01f29d7549f11cdd329d5ca8a2e163665f3a.tar.gz coreboot-56cf01f29d7549f11cdd329d5ca8a2e163665f3a.tar.bz2 coreboot-56cf01f29d7549f11cdd329d5ca8a2e163665f3a.zip |
This patch adds automatic fan control for the CPU fan on the m57sli
board.
This is done via the ec_init routine in a source file in the
mainboard/gigabyte/m57sli directory. A Config variable 'HAVE_FANCTL' has been
added to notify superio.c to get the ec_init externally.
I (Ward) have tested this on the PLCC and the SOIC/SPI version of this board.
It works.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r-- | src/config/Options.lb | 5 | ||||
-rw-r--r-- | src/mainboard/gigabyte/m57sli/Config.lb | 4 | ||||
-rw-r--r-- | src/mainboard/gigabyte/m57sli/Options.lb | 6 | ||||
-rw-r--r-- | src/mainboard/gigabyte/m57sli/fanctl.c | 57 | ||||
-rw-r--r-- | src/superio/ite/it8716f/superio.c | 4 |
5 files changed, 76 insertions, 0 deletions
diff --git a/src/config/Options.lb b/src/config/Options.lb index 7b22ea8692cc..9ba5f32eddf0 100644 --- a/src/config/Options.lb +++ b/src/config/Options.lb @@ -861,6 +861,11 @@ end # Misc device options ############################################### +define HAVE_FANCTL + default 0 + export used + comment "Include board specific FAN control initialization" +end define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 default 0 export used diff --git a/src/mainboard/gigabyte/m57sli/Config.lb b/src/mainboard/gigabyte/m57sli/Config.lb index 5f34c9eeb593..127ce0309b93 100644 --- a/src/mainboard/gigabyte/m57sli/Config.lb +++ b/src/mainboard/gigabyte/m57sli/Config.lb @@ -206,6 +206,10 @@ else end end +if HAVE_FANCTL + object fanctl.o +end + ## ## Setup RAM ## diff --git a/src/mainboard/gigabyte/m57sli/Options.lb b/src/mainboard/gigabyte/m57sli/Options.lb index 149bbde94c0f..88d311bf2475 100644 --- a/src/mainboard/gigabyte/m57sli/Options.lb +++ b/src/mainboard/gigabyte/m57sli/Options.lb @@ -115,6 +115,7 @@ uses WAIT_BEFORE_CPUS_INIT uses CONFIG_USE_PRINTK_IN_CAR +uses HAVE_FANCTL ### ### Build options ### @@ -140,6 +141,11 @@ default FAILOVER_SIZE=0x01000 default CONFIG_LB_MEM_TOPK=2048 ## +## Set-up automatic fan control +## +default HAVE_FANCTL=1 + +## ## Build code for the fallback boot ## default HAVE_FALLBACK_BOOT=1 diff --git a/src/mainboard/gigabyte/m57sli/fanctl.c b/src/mainboard/gigabyte/m57sli/fanctl.c new file mode 100644 index 000000000000..8b74014dbd84 --- /dev/null +++ b/src/mainboard/gigabyte/m57sli/fanctl.c @@ -0,0 +1,57 @@ +#include <arch/io.h> + +static void write_index(uint16_t port_base, uint8_t reg, uint8_t value) +{ + outb(reg, port_base); + outb(value, port_base + 1); +} + +static const struct { + uint8_t index, value; +} sequence[]= { + /* Set FAN_CTL control register (0x14) polarity to high, and + activate fans 1, 2 and 3. */ + { 0x14, 0x87}, + /* set the correct sensor types 1,2 thermistor; 3 diode */ + { 0x51, 0x1c}, + /* set the 'zero' voltage for diode type sensor */ + { 0x5c, 0x80}, +// { 0x56, 0xe5}, +// { 0x57, 0xe5}, + { 0x59, 0xe5}, + { 0x5c, 0x00}, + /* fan1 (controlled by temp3) control parameters */ + /* fan off limit */ + { 0x60, 0xff}, + /* fan start limit */ + { 0x61, 0x14}, + /* ???? */ +// { 0x62, 0x00}, + /* start PWM */ + { 0x63, 0x27}, + /* smooth and slope PWM */ + { 0x64, 0x90}, + /* direct-down and interval */ + { 0x65, 0x03}, + /* fan1 auto controlled by temp3 */ + { 0x15, 0x82}, + /* fan2 soft controlled, max speed */ + { 0x16, 0x7f}, + /* fan3 soft controlled, 75% speed */ + { 0x17, 0x60}, + /* all fans enable, fan1 ctl smart */ + { 0x13, 0x71} +}; + +#define ARRAYSIZE(x) sizeof x/sizeof *x + +/* + * Called from superio.c + */ +void init_ec(uint16_t base) +{ + int i; + for (i=0; i<ARRAYSIZE(sequence); i++) { + write_index(base, sequence[i].index, sequence[i].value); + } +} diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index be78639b870f..d0f0857e89f9 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -62,6 +62,9 @@ static uint8_t pnp_read_index(uint16_t port_base, uint8_t reg) return inb(port_base + 1); } +#ifdef HAVE_FANCTL +extern void init_ec(uint16_t base); +#else static void init_ec(uint16_t base) { uint8_t value; @@ -77,6 +80,7 @@ static void init_ec(uint16_t base) printk_debug("FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n", base + 0x14, value | 0x87); } +#endif static void it8716f_init(device_t dev) { |