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authorMatt DeVillier <matt.devillier@gmail.com>2021-11-11 08:46:36 -0600
committerFelix Held <felix-coreboot@felixheld.de>2023-07-31 14:12:04 +0000
commit58fd7f4acb487de9fdb1cac4dff79d409108799d (patch)
tree0806b4d196bc3fa3f028fcd7177d06a8b02129a9 /src
parentee615d67b39f82571dcff8823f5ee27eb938a668 (diff)
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mb/google/cyan: Disable unused devices in devicetree
These devices are not present/used on CYAN boards. Change-Id: I012b49562c2b932822823537032e2265901ddc81 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76799 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/cyan/devicetree.cb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb
index c987d3b58391..5b7ef9a53989 100644
--- a/src/mainboard/google/cyan/devicetree.cb
+++ b/src/mainboard/google/cyan/devicetree.cb
@@ -97,7 +97,7 @@ chip soc/intel/braswell
device pci 00.0 on end # 8086 2280 - SoC transaction router
device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
device pci 03.0 off end # 8086 22b8 - Camera and Image Processor
- device pci 0b.0 on end # 8086 22dc - Signal Processing Controller
+ device pci 0b.0 off end # 8086 22dc - Signal Processing Controller
device pci 10.0 on end # 8086 2294 - MMC Port
device pci 11.0 off end # 8086 0F15 - SDIO Port
device pci 12.0 on end # 8086 0F16 - SD Port
@@ -122,7 +122,7 @@ chip soc/intel/braswell
device pci 1e.0 on end # 8086 2286 - SIO - DMA
device pci 1e.1 off end # 8086 0F08 - PWM 1
device pci 1e.2 off end # 8086 0F09 - PWM 2
- device pci 1e.3 on end # 8086 228a - HSUART 1
+ device pci 1e.3 off end # 8086 228a - HSUART 1
device pci 1e.4 off end # 8086 228c - HSUART 2
device pci 1e.5 on end # 8086 228e - SPI 1
device pci 1e.6 off end # 8086 2290 - SPI 2