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| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-01-08 11:51:37 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-25 10:42:58 +0000 |
| commit | 591b0ff535d36f0f69e92c55fe465cbf70dcbfe4 (patch) | |
| tree | eeb0b9afd5eca479aa336afd6a0e3b05ca776b27 /src | |
| parent | 6d126acfac7ec8c13f9814c98d1016c64545cabd (diff) | |
| download | coreboot-591b0ff535d36f0f69e92c55fe465cbf70dcbfe4.tar.gz coreboot-591b0ff535d36f0f69e92c55fe465cbf70dcbfe4.tar.bz2 coreboot-591b0ff535d36f0f69e92c55fe465cbf70dcbfe4.zip | |
soc/intel/tigerlake: Configure ClkReq according to mainboard design
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board from NVMe
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I14997e0a7d03bf1a97d115cbf0a7ad2603ef9953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38285
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 388ac4264932..a4533c9e6c28 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -60,12 +60,15 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->PcieClkSrcUsage[i] = 0xff; } + memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, + sizeof(config->PcieClkSrcClkReq)); + m_cfg->PrmrrSize = config->PrmrrSize; m_cfg->EnableC6Dram = config->enable_c6dram; /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; - /* UART Debug Log*/ + /* UART Debug Log */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB; m_cfg->PcdIsaSerialUartBase = 0x0; |