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| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-04-03 00:42:22 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-04-20 06:03:54 +0000 |
| commit | 5c27182366ac1d699ea2e4cc7b28cb3fadc80f6e (patch) | |
| tree | dc565bc64184f7ef82ecbdf8b58203b510378e38 /src | |
| parent | cae98879962c7c90e93c373ad6255da099305f35 (diff) | |
| download | coreboot-5c27182366ac1d699ea2e4cc7b28cb3fadc80f6e.tar.gz coreboot-5c27182366ac1d699ea2e4cc7b28cb3fadc80f6e.tar.bz2 coreboot-5c27182366ac1d699ea2e4cc7b28cb3fadc80f6e.zip | |
mb/tglrvp: Configure intel common config
Configure lockdown and i2c speed setting.
BUG:b:151161585
BRANCH=none
TEST=build and boot tglrvp and check FSP logs to lockdown
parameters
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Id7a1e9bd94ff86faa390b5de0518e8b3cb668bff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40116
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 20 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 20 |
2 files changed, 40 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 82303c6ddf66..8b4f8f8bbfd1 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -128,6 +128,26 @@ chip soc/intel/tigerlake # Not disconnected/enumerable register "PchHdaIDispCodecDisconnect" = "0" + # Intel Common SoC Config + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 043185bfdd16..9b5774bd1c74 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -124,6 +124,26 @@ chip soc/intel/tigerlake # Not disconnected/enumerable register "PchHdaIDispCodecDisconnect" = "0" + # Intel Common SoC Config + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y |