TPM: Add tlcl_cr50_get_boot_mode

tlcl_cr50_get_boot_mode gets the boot mode from Cr50. The boot mode
tells coreboot/depthcharge whether booting the kernel is allowed or
not.

BUG=b:147298634, chromium:1045217, b:148259137
BRANCH=none
TEST=Verify software sync succeeds on Puff.

Signed-off-by: dnojiri <dnojiri@chromium.org>
Change-Id: Iadae848c4bf315f2131ff6aebcb35938307b5db4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40388
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 40 insertions, 0 deletions

diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c
index 45ade1a31416..a229dd17efdf 100644
--- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c
+++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c
@@ -335,6 +335,9 @@ static int marshal_cr50_vendor_command(struct obuf *ob, void *command_body)
 		 */
 		rc |= obuf_write_be16(ob, *sub_command);
 		break;
+	case TPM2_CR50_SUB_CMD_GET_BOOT_MODE:
+		rc |= obuf_write_be16(ob, *sub_command);
+		break;
 	default:
 		/* Unsupported subcommand. */
 		printk(BIOS_WARNING, "Unsupported cr50 subcommand: 0x%04x\n",
@@ -560,6 +563,8 @@ static int unmarshal_vendor_command(struct ibuf *ib,
 		return ibuf_read_be8(ib, &vcr->recovery_button_state);
 	case TPM2_CR50_SUB_CMD_TPM_MODE:
 		return ibuf_read_be8(ib, &vcr->tpm_mode);
+	case TPM2_CR50_SUB_CMD_GET_BOOT_MODE:
+		return ibuf_read_be8(ib, &vcr->boot_mode);
 	default:
 		printk(BIOS_ERR,
 		       "%s:%d - unsupported vendor command %#04x!\n",
diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h
index ade9b2787301..3f0c6545abe5 100644
--- a/src/security/tpm/tss/tcg-2.0/tss_structures.h
+++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h
@@ -349,6 +349,7 @@ struct vendor_command_response {
 		uint8_t num_restored_headers;
 		uint8_t recovery_button_state;
 		uint8_t tpm_mode;
+		uint8_t boot_mode;
 	};
 };
 
diff --git a/src/security/tpm/tss/vendor/cr50/cr50.c b/src/security/tpm/tss/vendor/cr50/cr50.c
index ec69df4ac9b9..ae2f7c25162c 100644
--- a/src/security/tpm/tss/vendor/cr50/cr50.c
+++ b/src/security/tpm/tss/vendor/cr50/cr50.c
@@ -107,6 +107,31 @@ uint32_t tlcl_cr50_get_tpm_mode(uint8_t *tpm_mode)
 	return TPM_SUCCESS;
 }
 
+uint32_t tlcl_cr50_get_boot_mode(uint8_t *boot_mode)
+{
+	struct tpm2_response *response;
+	uint16_t mode_command = TPM2_CR50_SUB_CMD_GET_BOOT_MODE;
+
+	printk(BIOS_DEBUG, "Reading cr50 boot mode\n");
+
+	response = tpm_process_command(TPM2_CR50_VENDOR_COMMAND, &mode_command);
+
+	if (!response)
+		return TPM_E_IOERROR;
+
+	if (response->hdr.tpm_code == VENDOR_RC_NO_SUCH_COMMAND)
+		/* Explicitly inform caller when command is not supported */
+		return TPM_E_NO_SUCH_COMMAND;
+
+	if (response->hdr.tpm_code)
+		/* Unexpected return code from Cr50 */
+		return TPM_E_IOERROR;
+
+	*boot_mode = response->vcr.boot_mode;
+
+	return TPM_SUCCESS;
+}
+
 uint32_t tlcl_cr50_immediate_reset(uint16_t timeout_ms)
 {
 	struct tpm2_response *response;
diff --git a/src/security/tpm/tss/vendor/cr50/cr50.h b/src/security/tpm/tss/vendor/cr50/cr50.h
index e3137630deee..0f917328567d 100644
--- a/src/security/tpm/tss/vendor/cr50/cr50.h
+++ b/src/security/tpm/tss/vendor/cr50/cr50.h
@@ -15,6 +15,7 @@
 #define TPM2_CR50_SUB_CMD_TURN_UPDATE_ON (24)
 #define TPM2_CR50_SUB_CMD_GET_REC_BTN (29)
 #define TPM2_CR50_SUB_CMD_TPM_MODE (40)
+#define TPM2_CR50_SUB_CMD_GET_BOOT_MODE (52)
 
 /* Cr50 vendor-specific error codes. */
 #define VENDOR_RC_ERR              0x00000500
@@ -79,6 +80,14 @@ uint32_t tlcl_cr50_get_recovery_button(uint8_t *recovery_button_state);
 uint32_t tlcl_cr50_get_tpm_mode(uint8_t *tpm_mode);
 
 /**
+ * CR50 specific TPM command sequence to query the current boot mode.
+ *
+ * Returns TPM_SUCCESS if boot mode is successfully retrieved.
+ * Returns TPM_E_* for errors.
+ */
+uint32_t tlcl_cr50_get_boot_mode(uint8_t *boot_mode);
+
+/**
  * CR50 specific TPM command sequence to trigger an immediate reset to the Cr50
  * device after the specified timeout in milliseconds.  A timeout of zero means
  * "IMMEDIATE REBOOT".