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| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-02-01 08:02:23 +0100 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-02-03 19:55:53 +0000 |
| commit | 64e2ecb36fd1d7b289cd9671dcfae2e335528d81 (patch) | |
| tree | a48c10aa42b234c85e8afaf28d0f11231e275e28 /src | |
| parent | a10a86d2bc8d3daf9394ccb0c7e0479ad1eec6e5 (diff) | |
| download | coreboot-64e2ecb36fd1d7b289cd9671dcfae2e335528d81.tar.gz coreboot-64e2ecb36fd1d7b289cd9671dcfae2e335528d81.tar.bz2 coreboot-64e2ecb36fd1d7b289cd9671dcfae2e335528d81.zip | |
soc/intel/apl: Move cpu cluster to chipset.cb
Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Diffstat (limited to 'src')
24 files changed, 2 insertions, 39 deletions
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index eec90bcd0d97..7801b0db33d3 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -1,5 +1,4 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[2]" = "3" # wifi/bt # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 2199ac091229..d24e67be5118 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index 70524972b114..f162519be4c7 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index bf404647e15c..79da9fd7a80c 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index 1ee9c3849c80..45007f09f0a6 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 7c775ef5bc35..ec9ea9c1148c 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb index ef361b0c8517..a983807f4f3a 100644 --- a/src/mainboard/intel/apollolake_rvp/devicetree.cb +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -7,8 +7,6 @@ chip soc/intel/apollolake register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on end - device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 45fb7361ba2f..551fc60d5267 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "3" # wifi/bt diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb index add83fe4377b..0a152b6a4a95 100644 --- a/src/mainboard/intel/leafhill/devicetree.cb +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -7,8 +7,6 @@ chip soc/intel/apollolake register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on end - device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb index add83fe4377b..0a152b6a4a95 100644 --- a/src/mainboard/intel/minnow3/devicetree.cb +++ b/src/mainboard/intel/minnow3/devicetree.cb @@ -7,8 +7,6 @@ chip soc/intel/apollolake register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on end - device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb index e77a1727673d..b3f9a6e67fa3 100644 --- a/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb @@ -2,8 +2,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - # Override USB port configuration register "usb_config_override" = "1" # USB 2.0 diff --git a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb index 7ce2480d55d3..a2a9df44c29c 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb +++ b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb @@ -5,7 +5,6 @@ chip soc/intel/apollolake register "enable_vtd" = "1" register "dptf_enable" = "1" - device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 00.1 on end # DPTF diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index dad319e9ff99..a08f053d8c58 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index b728438ed862..b515170ad03c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index 4fae59e38f96..56d93aa30ded 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 586d65e43430..1c5f7970ef09 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 40739df913f5..92bba650478c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index c48eb5a030c4..8223f68babca 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # 0:HS400(Default), 1:HS200, 2:DDR50 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb index ce716a0c8341..0a080c3a63a8 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb index 709d8e18b446..f1ace5a559de 100644 --- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb @@ -1,5 +1,4 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end # Graphics # TODO: diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index 96011ea2c67c..71932a64501c 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -1,5 +1,4 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end # Graphics # TODO: diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index 867f3a5180e4..4b0d5f79b170 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -20,7 +20,6 @@ chip soc/intel/apollolake # 0:HS400 (Default) 1:HS200 2:DDR50 register "emmc_host_max_speed" = "1" - device cpu_cluster 0 on end device domain 0 on subsystemid 0x8086 0x7270 inherit device pci 00.0 on end # - Host Bridge diff --git a/src/soc/intel/apollolake/chipset_apl.cb b/src/soc/intel/apollolake/chipset_apl.cb index 8a1b5018b6c4..b4f1659899c5 100644 --- a/src/soc/intel/apollolake/chipset_apl.cb +++ b/src/soc/intel/apollolake/chipset_apl.cb @@ -1,4 +1,5 @@ chip soc/intel/apollolake + device cpu_cluster 0 on end device domain 0 on device pci 00.0 alias system_agent on end # Host Bridge device pci 00.1 alias dptf on end # DPTF diff --git a/src/soc/intel/apollolake/chipset_glk.cb b/src/soc/intel/apollolake/chipset_glk.cb index 00436302fb7e..07eecf5b1773 100644 --- a/src/soc/intel/apollolake/chipset_glk.cb +++ b/src/soc/intel/apollolake/chipset_glk.cb @@ -1,4 +1,5 @@ chip soc/intel/apollolake + device cpu_cluster 0 on end device domain 0 on device pci 00.0 alias system_agent on end # Host Bridge device pci 00.1 alias dptf on end # DPTF |