Convert all Intel 82371AB/EB/MB based boards to TINY_BOOTBLOCK.

Also:

Unfortunately Intel 440BX + 82371AB/EB/MB boards can have their ISA device
on various PCI bus:device.function locations.
Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.

Thus, instead of hardcoding PCI bus:device.function numbers such as
PCI_DEV(0, 7, 0), we now simply find the ISA device via PCI IDs, which
works the same on all boards.

As an additional benefit this patch also gets rid of one .c file include
in romstage.c.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

23 files changed, 47 insertions, 81 deletions

diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c
index a55997fae9c0..b32f10b102ef 100644
--- a/src/mainboard/a-trend/atc-6220/romstage.c
+++ b/src/mainboard/a-trend/atc-6220/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -53,9 +52,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c
index abfe3c4a1598..4384c2387fe9 100644
--- a/src/mainboard/a-trend/atc-6240/romstage.c
+++ b/src/mainboard/a-trend/atc-6240/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -53,9 +52,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c
index d2cc87f89283..ca2a56e3cf30 100644
--- a/src/mainboard/abit/be6-ii_v2_0/romstage.c
+++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -56,9 +55,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge at 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c
index 1264dd02cbca..2fc26aba1632 100644
--- a/src/mainboard/asus/p2b-d/romstage.c
+++ b/src/mainboard/asus/p2b-d/romstage.c
@@ -27,7 +27,6 @@
 #include <stdlib.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -56,9 +55,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c
index 2bb1a46bbdd1..002ff93ea949 100644
--- a/src/mainboard/asus/p2b-ds/romstage.c
+++ b/src/mainboard/asus/p2b-ds/romstage.c
@@ -27,7 +27,6 @@
 #include <stdlib.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -56,9 +55,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c
index baf2db42c316..40277c459f87 100644
--- a/src/mainboard/asus/p2b-f/romstage.c
+++ b/src/mainboard/asus/p2b-f/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -56,9 +55,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c
index 0b653a4a6b4c..a1018fbaa81d 100644
--- a/src/mainboard/asus/p2b-ls/romstage.c
+++ b/src/mainboard/asus/p2b-ls/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -55,9 +54,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c
index e3a48b3b6113..b32f10b102ef 100644
--- a/src/mainboard/asus/p2b/romstage.c
+++ b/src/mainboard/asus/p2b/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -53,9 +52,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c
index 31b401ac96c9..8d8c0b39d873 100644
--- a/src/mainboard/asus/p3b-f/romstage.c
+++ b/src/mainboard/asus/p3b-f/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_pm.c"
 #include "northbridge/intel/i440bx/raminit.h"
@@ -88,9 +87,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
-
 	enable_smbus();
 	enable_pm();
 
diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c
index a901c38541fc..67d7b92ca92e 100644
--- a/src/mainboard/azza/pt-6ibd/romstage.c
+++ b/src/mainboard/azza/pt-6ibd/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -56,9 +55,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c
index fb60168036cf..d00fc773eacc 100644
--- a/src/mainboard/biostar/m6tba/romstage.c
+++ b/src/mainboard/biostar/m6tba/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -54,9 +53,6 @@ void main(unsigned long bist)
 	report_bist_failure(bist);
 	enable_smbus();
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	dump_spd_registers();
 	sdram_set_registers();
 	sdram_set_spd_registers();
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
index 42c43c86cf7f..66ef32fa66ad 100644
--- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
+++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -56,9 +55,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 14, 0)); /* ISA bridge is 00:14.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c
index 040e762d24ea..13e1ff71d318 100644
--- a/src/mainboard/gigabyte/ga-6bxc/romstage.c
+++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -54,9 +53,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c
index aafd39453c3d..e60ca46fa8f3 100644
--- a/src/mainboard/gigabyte/ga-6bxe/romstage.c
+++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -55,9 +54,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c
index aaa03ee52d27..5dde6c4e556f 100644
--- a/src/mainboard/msi/ms6119/romstage.c
+++ b/src/mainboard/msi/ms6119/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -53,9 +52,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c
index 2f84fbffd607..dfa9c993aeb7 100644
--- a/src/mainboard/msi/ms6147/romstage.c
+++ b/src/mainboard/msi/ms6147/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -53,9 +52,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c
index 45c97eea6acb..4e25f093b769 100644
--- a/src/mainboard/msi/ms6156/romstage.c
+++ b/src/mainboard/msi/ms6156/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -53,9 +52,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c
index 57d3dede8695..f508fc6dc6a0 100644
--- a/src/mainboard/nokia/ip530/romstage.c
+++ b/src/mainboard/nokia/ip530/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -53,9 +52,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0) ); /* ISA bridge at 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
index 901d271656ef..c608aac86ab9 100644
--- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
+++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -54,9 +53,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c
index 8b9ae8db14e6..599dcdfc85db 100644
--- a/src/mainboard/tyan/s1846/romstage.c
+++ b/src/mainboard/tyan/s1846/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
@@ -53,9 +52,6 @@ void main(unsigned long bist)
 	console_init();
 	report_bist_failure(bist);
 
-	/* Enable access to the full ROM chip, needed very early by CBFS. */
-	i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
-
 	enable_smbus();
 	dump_spd_registers();
 	sdram_set_registers();
diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig
index bda72cf2f443..cd457c2e3766 100644
--- a/src/southbridge/intel/i82371eb/Kconfig
+++ b/src/southbridge/intel/i82371eb/Kconfig
@@ -1,4 +1,10 @@
 config SOUTHBRIDGE_INTEL_I82371EB
 	bool
 	select IOAPIC
+	select TINY_BOOTBLOCK
+
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+	string
+	default "southbridge/intel/i82371eb/bootblock.c"
+	depends on SOUTHBRIDGE_INTEL_I82371EB
 
diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c
new file mode 100644
index 000000000000..c818691639e9
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/bootblock.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
+
+static void bootblock_southbridge_init(void)
+{
+	i82371eb_enable_rom();
+}
diff --git a/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c b/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c
index 5b12e462be3c..46b0144f28e0 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c
@@ -19,11 +19,25 @@
  */
 
 #include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
 #include "i82371eb.h"
 
-static void i82371eb_enable_rom(device_t dev)
+static void i82371eb_enable_rom(void)
 {
 	u16 reg16;
+	device_t dev;
+
+	/*
+	 * Note: The Intel 82371AB/EB/MB ISA device can be on different
+	 * PCI bus:device.function locations on different boards.
+	 * Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.
+	 * But scanning for the PCI IDs (instead of hardcoding
+	 * bus/device/function numbers) works on all boards.
+	 */
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
+				       PCI_DEVICE_ID_INTEL_82371AB_ISA), 0);
 
 	/* Enable access to the whole ROM, disable ROM write access. */
 	reg16 = pci_read_config16(dev, XBCS);