soc/mediatek/mt8195: Initialize watchdog

MT8195 requires writing speical value to mode register to clear
status register. This value is invalid on other platforms. We can
do this safely in the common watchdog driver.

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Iba5b41f426fc38719bb343a220e0724bff229c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

6 files changed, 18 insertions, 1 deletions

diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig
index 543bc02d1363..29cd2109f9f7 100644
--- a/src/soc/mediatek/common/Kconfig
+++ b/src/soc/mediatek/common/Kconfig
@@ -29,4 +29,9 @@ config MEMORY_TEST
 	  This option enables memory basic compare test to verify the DRAM read
 	  or write is as expected.
 
+config CLEAR_WDT_MODE_REG
+	bool
+	help
+	  Enable this option to clear WTD mode register explicitly.
+
 endif
diff --git a/src/soc/mediatek/common/include/soc/wdt.h b/src/soc/mediatek/common/include/soc/wdt.h
index 44ab5c770058..5847d4953f84 100644
--- a/src/soc/mediatek/common/include/soc/wdt.h
+++ b/src/soc/mediatek/common/include/soc/wdt.h
@@ -21,6 +21,7 @@ struct mtk_wdt_regs {
 /* WDT_MODE */
 enum {
 	MTK_WDT_MODE_KEY	= 0x22000000,
+	MTK_WDT_CLR_STATUS	= 0x230001FF,
 	MTK_WDT_MODE_DUAL_MODE	= 1 << 6,
 	MTK_WDT_MODE_IRQ	= 1 << 3,
 	MTK_WDT_MODE_EXTEN	= 1 << 2,
diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c
index e9edb48ef57d..44a9ce50b6ee 100644
--- a/src/soc/mediatek/common/wdt.c
+++ b/src/soc/mediatek/common/wdt.c
@@ -9,9 +9,12 @@ int mtk_wdt_init(void)
 {
 	uint32_t wdt_sta;
 
-	/* Write Mode register will clear status register */
+	/* Writing mode register will clear status register */
 	wdt_sta = read32(&mtk_wdt->wdt_status);
 
+	if (CONFIG(CLEAR_WDT_MODE_REG))
+		write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS);
+
 	printk(BIOS_INFO, "WDT: Last reset was ");
 	if (wdt_sta & MTK_WDT_STA_HW_RST) {
 		printk(BIOS_INFO, "hardware watchdog\n");
diff --git a/src/soc/mediatek/mt8195/Kconfig b/src/soc/mediatek/mt8195/Kconfig
index 090ca2fe1792..76329cd2e1eb 100644
--- a/src/soc/mediatek/mt8195/Kconfig
+++ b/src/soc/mediatek/mt8195/Kconfig
@@ -6,6 +6,8 @@ config SOC_MEDIATEK_MT8195
 	select ARCH_ROMSTAGE_ARMV8_64
 	select ARCH_RAMSTAGE_ARMV8_64
 	select HAVE_UART_SPECIAL
+	select SOC_MEDIATEK_COMMON
+	select CLEAR_WDT_MODE_REG
 
 if SOC_MEDIATEK_MT8195
 
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index ab7561f2d143..3fa1d1993d96 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -5,22 +5,26 @@ bootblock-y += ../common/mmu_operations.c
 bootblock-$(CONFIG_SPI_FLASH) += spi.c
 bootblock-y += ../common/timer.c
 bootblock-y += ../common/uart.c
+bootblock-y += ../common/wdt.c
 
 verstage-$(CONFIG_SPI_FLASH) += spi.c
 verstage-y += ../common/timer.c
 verstage-y += ../common/uart.c
+verstage-y += ../common/wdt.c
 
 romstage-y += ../common/cbmem.c
 romstage-y += emi.c
 romstage-$(CONFIG_SPI_FLASH) += spi.c
 romstage-y += ../common/timer.c
 romstage-y += ../common/uart.c
+romstage-y += ../common/wdt.c
 
 ramstage-y += emi.c
 ramstage-$(CONFIG_SPI_FLASH) += spi.c
 ramstage-y += soc.c
 ramstage-y += ../common/timer.c
 ramstage-y += ../common/uart.c
+ramstage-y += ../common/wdt.c
 
 CPPFLAGS_common += -Isrc/soc/mediatek/mt8195/include
 CPPFLAGS_common += -Isrc/soc/mediatek/common/include
diff --git a/src/soc/mediatek/mt8195/bootblock.c b/src/soc/mediatek/mt8195/bootblock.c
index f48e78c309a3..770c6031dabf 100644
--- a/src/soc/mediatek/mt8195/bootblock.c
+++ b/src/soc/mediatek/mt8195/bootblock.c
@@ -2,8 +2,10 @@
 
 #include <bootblock_common.h>
 #include <soc/mmu_operations.h>
+#include <soc/wdt.h>
 
 void bootblock_soc_init(void)
 {
 	mtk_mmu_init();
+	mtk_wdt_init();
 }