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| author | Raihow Shi <raihow_shi@wistron.corp-partner.google.com> | 2022-08-19 13:38:05 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-08-21 14:53:22 +0000 |
| commit | 6eda41743eec410f2f927ebe16844cbfa24b08bb (patch) | |
| tree | 90db024c0e909f443559e43dbf7817b0d8565195 /src | |
| parent | 50b45d35f097d017e18e27d43c65f7e458df7e4e (diff) | |
| download | coreboot-6eda41743eec410f2f927ebe16844cbfa24b08bb.tar.gz coreboot-6eda41743eec410f2f927ebe16844cbfa24b08bb.tar.bz2 coreboot-6eda41743eec410f2f927ebe16844cbfa24b08bb.zip | |
mb/google/brask/variants/moli: Support DPTF oem_variables
Enable DPTF oem_variables and override based on CPU match id.
BUG=b:236294162
TEST=emerge-brask coreboot and check the value in odvp0 is correct.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ic935ec42f4de0cbec996da37b44f354978fe4b62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66907
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/moli/overridetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/moli/ramstage.c | 32 |
2 files changed, 36 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index 9f2c22bda2b9..e5a9a0439f1f 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -88,6 +88,10 @@ chip soc/intel/alderlake } }" + register "oem_data.oem_variables" = "{ + [0] = 0x1 + }" + ## Fan Performance Control (Percent, Speed, Noise, Power) register "controls.fan_perf" = "{ [0] = { 90, 6700, 220, 2200, }, diff --git a/src/mainboard/google/brya/variants/moli/ramstage.c b/src/mainboard/google/brya/variants/moli/ramstage.c index 77bf3aea7ad5..ea863c52f5fd 100644 --- a/src/mainboard/google/brya/variants/moli/ramstage.c +++ b/src/mainboard/google/brya/variants/moli/ramstage.c @@ -5,10 +5,12 @@ #include <device/device.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/pci.h> #include <drivers/intel/gma/opregion.h> #include <ec/google/chromeec/ec.h> #include <fw_config.h> #include <intelblocks/power_limit.h> +#include <drivers/intel/dptf/chip.h> const struct cpu_power_limits limits[] = { /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ @@ -26,6 +28,35 @@ const struct system_power_limits sys_limits[] = { { PCI_DID_INTEL_ADL_P_ID_5, 28, 135 }, }; +static void update_oem_variables(void) +{ + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + uint16_t mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + const struct device *policy_dev = DEV_PTR(dptf_policy); + struct drivers_intel_dptf_config *config = policy_dev->chip_info; + + switch (mch_id) { + case PCI_DID_INTEL_ADL_P_ID_5: + config->oem_data.oem_variables[0] = 0; + break; + + case PCI_DID_INTEL_ADL_P_ID_6: + config->oem_data.oem_variables[0] = 1; + break; + + case PCI_DID_INTEL_ADL_P_ID_7: + config->oem_data.oem_variables[0] = 1; + break; + + case PCI_DID_INTEL_ADL_P_ID_10: + config->oem_data.oem_variables[0] = 1; + break; + + default: + config->oem_data.oem_variables[0] = 1; + } +} + const struct psys_config psys_config = { .efficiency = 97, .psys_imax_ma = 11000, @@ -37,4 +68,5 @@ void variant_devtree_update(void) size_t total_entries = ARRAY_SIZE(limits); variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); variant_update_power_limits(limits, total_entries); + update_oem_variables(); } |