diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-02-24 13:43:39 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-04 15:43:30 +0000 |
| commit | 79ccc6933284ca02d17d9e1eda9a531ce43e1f65 (patch) | |
| tree | 49fe1b78916338575b1a6bec931e2fb885cc311a /src | |
| parent | f3161df2eba8d61445372a9c732c61a1947064bd (diff) | |
| download | coreboot-79ccc6933284ca02d17d9e1eda9a531ce43e1f65.tar.gz coreboot-79ccc6933284ca02d17d9e1eda9a531ce43e1f65.tar.bz2 coreboot-79ccc6933284ca02d17d9e1eda9a531ce43e1f65.zip | |
src: capitalize 'PCIe'
Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
28 files changed, 30 insertions, 30 deletions
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index be7c6354713f..658434d2c8d6 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -100,7 +100,7 @@ void amd_initenv(void) PciValue |= 0x80000000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - /* Initialize GMM Base Address for Pcie Mode + /* Initialize GMM Base Address for PCIe Mode * Modify B0D1F0x18 */ PciAddress.Address.Bus = 0; @@ -112,7 +112,7 @@ void amd_initenv(void) PciValue |= 0x96000000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); - /* Initialize FB Base Address for Pcie Mode + /* Initialize FB Base Address for PCIe Mode * Modify B0D1F0x10 */ PciAddress.Address.Register = 0x10; diff --git a/src/mainboard/asrock/e350m1/acpi/routing.asl b/src/mainboard/asrock/e350m1/acpi/routing.asl index 537bcacaa181..06750124e265 100644 --- a/src/mainboard/asrock/e350m1/acpi/routing.asl +++ b/src/mainboard/asrock/e350m1/acpi/routing.asl @@ -199,7 +199,7 @@ Scope(\_SB) { /* Package(){0x00140005, 1, 0, 17 }, */ /* Package(){0x00140006, 1, 0, 17 }, */ - /* TODO: pcie */ + /* TODO: PCIe */ Package(){0x0015FFFF, 0, 0, 16 }, Package(){0x0015FFFF, 1, 0, 17 }, Package(){0x0015FFFF, 2, 0, 18 }, diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl index c0aef87a15c5..38ba14279504 100644 --- a/src/mainboard/asus/f2a85-m/acpi/routing.asl +++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl @@ -78,7 +78,7 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 21 Pcie Bridge */ + /* Bus 0, Dev 21 PCIe Bridge */ Package(){0x0015FFFF, 0, INTA, 0 }, Package(){0x0015FFFF, 1, INTB, 0 }, Package(){0x0015FFFF, 2, INTC, 0 }, diff --git a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl index 447d9923515b..af05ec6848b9 100644 --- a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl +++ b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl @@ -200,7 +200,7 @@ Scope(\_SB) { /* Package(){0x00140005, 1, 0, 17 }, */ /* Package(){0x00140006, 1, 0, 17 }, */ - /* TODO: pcie */ + /* TODO: PCIe */ Package(){0x0015FFFF, 0, 0, 16 }, Package(){0x0015FFFF, 1, 0, 17 }, Package(){0x0015FFFF, 2, 0, 18 }, diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl index 22c45501a602..a1ce8606827c 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl @@ -90,7 +90,7 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 21 Pcie Bridge */ + /* Bus 0, Dev 21 PCIe Bridge */ Package(){0x0015FFFF, 0, INTA, 0 }, Package(){0x0015FFFF, 1, INTB, 0 }, Package(){0x0015FFFF, 2, INTC, 0 }, diff --git a/src/mainboard/lenovo/g505s/acpi/routing.asl b/src/mainboard/lenovo/g505s/acpi/routing.asl index 22c45501a602..a1ce8606827c 100644 --- a/src/mainboard/lenovo/g505s/acpi/routing.asl +++ b/src/mainboard/lenovo/g505s/acpi/routing.asl @@ -90,7 +90,7 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 21 Pcie Bridge */ + /* Bus 0, Dev 21 PCIe Bridge */ Package(){0x0015FFFF, 0, INTA, 0 }, Package(){0x0015FFFF, 1, INTB, 0 }, Package(){0x0015FFFF, 2, INTC, 0 }, diff --git a/src/mainboard/msi/ms7721/acpi/routing.asl b/src/mainboard/msi/ms7721/acpi/routing.asl index 0af6b42cad54..5443dd530745 100644 --- a/src/mainboard/msi/ms7721/acpi/routing.asl +++ b/src/mainboard/msi/ms7721/acpi/routing.asl @@ -71,7 +71,7 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - /* Bus 0, Dev 21 Pcie Bridge */ + /* Bus 0, Dev 21 PCIe Bridge */ Package(){0x0015FFFF, 0, INTA, 0 }, Package(){0x0015FFFF, 1, INTB, 0 }, Package(){0x0015FFFF, 2, INTC, 0 }, diff --git a/src/mainboard/pcengines/apu1/acpi/routing.asl b/src/mainboard/pcengines/apu1/acpi/routing.asl index 9a63d7223277..79ebef3f037d 100644 --- a/src/mainboard/pcengines/apu1/acpi/routing.asl +++ b/src/mainboard/pcengines/apu1/acpi/routing.asl @@ -162,7 +162,7 @@ Scope(\_SB) { /* Package(){0x00140005, 1, 0, 17 }, */ /* Package(){0x00140006, 1, 0, 17 }, */ - /* TODO: pcie */ + /* TODO: PCIe */ Package(){0x0015FFFF, 0, 0, 16 }, Package(){0x0015FFFF, 1, 0, 17 }, Package(){0x0015FFFF, 2, 0, 18 }, diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index 703e20fa8a96..a8b0f5371910 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -99,7 +99,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 4a89eb967eba..853272850340 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -83,7 +83,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 6dc0346b230f..6b6c28d73195 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -163,7 +163,7 @@ static u8 all_ports_no_dev_present(struct device *dev) dev->path.pci.devfn &= ~0x7; dev->path.pci.devfn |= func; - /* is pcie device there */ + /* is PCIe device there */ if (pci_read_config32(dev, 0) == 0xFFFFFFFF) continue; diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index a67117da5f69..41f1854d30fb 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -101,7 +101,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 33800ef8fd9f..f4cd8f2444f2 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -86,7 +86,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl index 22a22e3ed160..87c053bc2a5d 100644 --- a/src/soc/intel/broadwell/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/acpi/globalnvs.asl @@ -91,7 +91,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 456fda6fa6f1..ea64341e58b4 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -75,7 +75,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd2; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 752ec1f315e5..330555c0c0a4 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -180,7 +180,7 @@ struct soc_intel_cannonlake_config { /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe output clocks type to Pcie devices. + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index d05e76bcf935..75f179ec6748 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -53,7 +53,7 @@ void smm_southbridge_enable_smi(void) { printk(BIOS_DEBUG, "Enabling SMIs.\n"); - /* Configure events Disable pcie wake. */ + /* Configure events Disable PCIe wake. */ enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); disable_gpe(PME_B0_EN); diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 569160f41f0b..56f89db5e714 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -134,7 +134,7 @@ struct soc_intel_icelake_config { /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe output clocks type to Pcie devices. + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index e17b2604cf9a..8aeb5a37f01d 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -106,7 +106,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index b189a16a05ab..2c3d3a59c83c 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -226,7 +226,7 @@ struct soc_intel_skylake_config { u8 PchDciEn; /* - * Pcie Root Port configuration: + * PCIe Root Port configuration: * each element of array corresponds to * respective PCIe root port. */ diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index d5f62f63fc6c..24e4cf1a2a07 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -88,7 +88,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 9eee97d53bff..e57abe857bac 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -114,7 +114,7 @@ struct soc_intel_tigerlake_config { /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe output clocks type to Pcie devices. + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 4b54d61b6612..5f41f441f500 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -166,7 +166,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index a6b0bdbc553f..0ec0c05cb01d 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -138,7 +138,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 5c2b130b7e6f..7c672b3cb598 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -351,8 +351,8 @@ static void pch_pcie_enable(struct device *dev) * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1 * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1 * - * This check is done here instead of pcie driver - * because the pcie driver enable() handler is not + * This check is done here instead of PCIe driver + * because the PCIe driver enable() handler is not * called unless the device is enabled. */ if ((PCI_FUNC(dev->path.pci.devfn) == 0 || diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index a95639894fd1..a0422f2bed33 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -137,7 +137,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index fddfa701afbe..3c873a2e60e5 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -161,7 +161,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PAVP, 8, // 0xe9 - IGD PAVP data Offset (0xeb), OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native pcie support + NPCE, 8, // 0xec - native PCIe support PLFL, 8, // 0xed - platform flavor BREV, 8, // 0xee - board revision DPBM, 8, // 0xef - digital port b mode diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 3aca7bbda385..34c2537e2ef6 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -114,7 +114,7 @@ typedef struct global_nvs_t { u8 pavp; /* 0xe9 - IGD PAVP data */ u8 rsvd12; /* 0xea - rsvd */ u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native pcie support */ + u8 npce; /* 0xec - native PCIe support */ u8 plfl; /* 0xed - platform flavor */ u8 brev; /* 0xee - board revision */ u8 dpbm; /* 0xef - digital port b mode */ |