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| author | Keith Hui <buurin@gmail.com> | 2020-01-11 13:53:10 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-03 07:35:13 +0000 |
| commit | 7af59f709a89d20c1691d1a7316b136c7024aaf9 (patch) | |
| tree | ed4529d9da847fa058c7eca8dccf9ab58f36a647 /src | |
| parent | eaba79cc66176ed9d9be23bce122b9d7bc238ed6 (diff) | |
| download | coreboot-7af59f709a89d20c1691d1a7316b136c7024aaf9.tar.gz coreboot-7af59f709a89d20c1691d1a7316b136c7024aaf9.tar.bz2 coreboot-7af59f709a89d20c1691d1a7316b136c7024aaf9.zip | |
sb/intel/i82371eb: Enable upper NVRAM bank
Change-Id: I9ad127ca4394e27fc055ddf03012a195cb03bd94
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/i82371eb/bootblock.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 711b317e168f..581db816a8e8 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -61,4 +61,7 @@ void bootblock_early_southbridge_init(void) reg16 |= LOWER_BIOS_ENABLE | EXT_BIOS_ENABLE | EXT_BIOS_ENABLE_1MB; reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */ pci_write_config16(dev, XBCS, reg16); + + /* Enable (RTC and) upper NVRAM bank. */ + pci_write_config8(dev, RTCCFG, RTC_POS_DECODE | UPPER_RAM_EN | RTC_ENABLE); } |