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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-09-21 08:28:23 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-09-22 18:31:03 +0000 |
| commit | 7eb0157fca33865783c1cc3c8e5cb2e327e551d7 (patch) | |
| tree | 537e678e9142692b9d391da13207b05ad19ba036 /src | |
| parent | c88e370f851e686b5998fb3a0c44d7ace6dae7c3 (diff) | |
| download | coreboot-7eb0157fca33865783c1cc3c8e5cb2e327e551d7.tar.gz coreboot-7eb0157fca33865783c1cc3c8e5cb2e327e551d7.tar.bz2 coreboot-7eb0157fca33865783c1cc3c8e5cb2e327e551d7.zip | |
device/dram/ddr2.c: Decoding byte[12] bit7 as self refresh flag
"Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3)" note
4 says bit7 of byte 12 indicates whether the assembly supports self
refresh.
This patch decodes this and modifies decoding tRR accordingly.
Change-Id: I091121a5d08159cea4befdedb5f3a92ce132c6e5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/device/dram/ddr2.c | 17 | ||||
| -rw-r--r-- | src/include/device/dram/ddr2.h | 2 |
2 files changed, 12 insertions, 7 deletions
diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 2dab68175445..d524238b222f 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -188,26 +188,26 @@ static u32 spd_decode_quarter_time(u8 c) */ static int spd_decode_tRR_time(u32 *tRR, u8 c) { - switch (c) { + switch (c & ~0x80) { default: printk(BIOS_WARNING, "Invalid tRR value 0x%x\n", c); return CB_ERR; - case 0x80: + case 0x0: *tRR = 15625 << 8; break; - case 0x81: + case 0x1: *tRR = 15625 << 6; break; - case 0x82: + case 0x2: *tRR = 15625 << 7; break; - case 0x83: + case 0x3: *tRR = 15625 << 9; break; - case 0x84: + case 0x4: *tRR = 15625 << 10; break; - case 0x85: + case 0x5: *tRR = 15625 << 11; break; } @@ -545,6 +545,9 @@ int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]) /* Refresh rate in us */ if (spd_decode_tRR_time(&dimm->tRR, spd[12]) != CB_SUCCESS) ret = SPD_STATUS_INVALID_FIELD; + dimm->flags.self_refresh = (spd[12] >> 7) & 1; + printram("The assembly supports self refresh: %s\n", + dimm->flags.self_refresh ? "true", "false"); /* Number of PLLs on DIMM */ if (dimm->rev >= 0x11) diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index ea9b3ba5355b..288c10298a3e 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -119,6 +119,8 @@ union dimm_flags_st { unsigned bl4:1; /* DIMM Package is stack */ unsigned stacked:1; + /* the assembly supports self refresh */ + unsigned self_refresh:1; }; unsigned int raw; }; |