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| author | Sean Rhodes <sean@starlabs.systems> | 2022-06-08 15:00:26 +0100 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-09-19 14:55:23 +0000 |
| commit | 7ef5376123d4d0ebb811795fcee1de7066f65a0f (patch) | |
| tree | 412899183c7d8c8f27ac09c78e053074afd24349 /src | |
| parent | d6695626631a86d9613ea7c34ff0e898fbfa443c (diff) | |
| download | coreboot-7ef5376123d4d0ebb811795fcee1de7066f65a0f.tar.gz coreboot-7ef5376123d4d0ebb811795fcee1de7066f65a0f.tar.bz2 coreboot-7ef5376123d4d0ebb811795fcee1de7066f65a0f.zip | |
soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown
Configure FSP S UPDs to allow coreboot to handle the lockdown.
The main change here is setting `Write Protection Support` to 0,
as the default is Enabled, which shouldn't allow writes (even though
it seems to).
The UPDs are identical on APL and GLK, but all ones configured
in this patch have been there since their initial releases.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I35185b498315511f3236758caebfe2f9c28fd04a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65039
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index da2d00adb75d..5bee9bfdbb78 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -16,6 +16,7 @@ #include <intelblocks/p2sb.h> #include <intelblocks/power_limit.h> #include <intelblocks/xdci.h> +#include <intelpch/lockdown.h> #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> @@ -697,11 +698,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); - /* Disable setting of EISS bit in FSP. */ - silconfig->SpiEiss = 0; - - /* Disable FSP from locking access to the RTC NVRAM */ - silconfig->RtcLock = 0; + /* coreboot handles the lockdown */ + silconfig->LockDownGlobalSmi = 0; + silconfig->BiosLock = 0; + silconfig->BiosInterface = 0; + silconfig->WriteProtectionEnable[0] = 0; + silconfig->SpiEiss = 0; + silconfig->RtcLock = 0; /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; |