skylake: align power management names with hardware

Some of the field and register names in the power management
code were not reflecting current chipset documentation. While
in there fix 0-sized array in the power_state structure. Lastly,
log the entire STD GPE register for visibility in elog. It reports
as an extension of other GPIO wake events.

BUG=None
BRANCH=None
TEST=Built and booted.

Change-Id: I57a621a418f90103ff92ddbf747e71a11d517c9a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ed15cc7d0aeee8070e134ed03e28fced9361c00e
Original-Change-Id: I19f9463c87e9472608e69d143932e66ea2b3c3e1
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288296
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11070
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

3 files changed, 16 insertions, 12 deletions

diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c
index 3ae0890c336c..45f7b71ec239 100644
--- a/src/soc/intel/skylake/elog.c
+++ b/src/soc/intel/skylake/elog.c
@@ -64,14 +64,12 @@ static void pch_log_wake_source(struct chipset_power_state *ps)
 	if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)
 		elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
 
-	/* GPIO27 */
-	if (ps->gpe0_sts[GPE_STD] & GP27_STS)
-		elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, 27);
-
 	/* Log GPIO events in set 1-3 */
 	pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0);
 	pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32);
-	pch_log_gpio_gpe(ps->gpe0_sts[GPE_94_64], ps->gpe0_en[GPE_94_64], 64);
+	pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64);
+	/* Treat the STD as an extension of GPIO to obtain visibility. */
+	pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96);
 }
 
 static void pch_log_power_and_resets(struct chipset_power_state *ps)
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 6b75641178e5..0475e20d78e4 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -86,10 +86,12 @@
 #define GPE0_STS(x)		(0x80 + (x * 4))
 #define  GPE_31_0		0	/* 0x80/0x90 = GPE[31:0] */
 #define  GPE_63_32		1	/* 0x84/0x94 = GPE[63:32] */
-#define  GPE_94_64		2	/* 0x88/0x98 = GPE[94:64] */
+#define  GPE_95_64		2	/* 0x88/0x98 = GPE[95:64] */
 #define  GPE_STD		3	/* 0x8c/0x9c = Standard GPE */
 #define   WADT_STS		(1 << 18)
-#define   GP27_STS		(1 << 16)
+#define   LAN_WAK_STS		(1 << 16)
+#define   GPIO_T2_STS		(1 << 15)
+#define   ESPI_STS		(1 << 14)
 #define   PME_B0_STS		(1 << 13)
 #define   ME_SCI_STS		(1 << 12)
 #define   PME_STS		(1 << 11)
@@ -101,7 +103,9 @@
 #define   HOT_PLUG_STS		(1 << 1)
 #define GPE0_EN(x)		(0x90 + (x * 4))
 #define   WADT_EN		(1 << 18)
-#define   GP27_EN		(1 << 16)
+#define   LAN_WAK_EN		(1 << 16)
+#define   GPIO_T2_EN		(1 << 15)
+#define   ESPI_EN		(1 << 14)
 #define   PME_B0_EN		(1 << 13)
 #define   ME_SCI_EN		(1 << 12)
 #define   PME_EN		(1 << 11)
@@ -129,7 +133,7 @@ struct chipset_power_state {
 	uint32_t gpe0_en[4];
 	uint32_t gen_pmcon_a;
 	uint32_t gen_pmcon_b;
-	uint32_t gblrst_cause[0];
+	uint32_t gblrst_cause[2];
 	uint32_t prev_sleep_state;
 } __attribute__ ((packed));
 
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 85dc1b3fda53..e5d4a2ee1999 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -396,13 +396,15 @@ u32 clear_gpe_status(void)
 		[11] = "PME",
 		[12] = "ME",
 		[13] = "PME_B0",
-		[16] = "GPIO27",
+		[14] = "eSPI",
+		[15] = "GPIO Tier-2",
+		[16] = "LAN_WAKE",
 		[18] = "WADT"
 	};
 
 	print_gpe_gpio(reset_gpe(GPE0_STS(GPE_31_0), GPE0_EN(GPE_31_0)), 0);
 	print_gpe_gpio(reset_gpe(GPE0_STS(GPE_63_32), GPE0_EN(GPE_63_32)), 32);
-	print_gpe_gpio(reset_gpe(GPE0_STS(GPE_94_64), GPE0_EN(GPE_94_64)), 64);
+	print_gpe_gpio(reset_gpe(GPE0_STS(GPE_95_64), GPE0_EN(GPE_95_64)), 64);
 	return print_gpe_status(reset_gpe(GPE0_STS(GPE_STD), GPE0_EN(GPE_STD)),
 				gpe0_sts_3_bits);
 }
@@ -412,7 +414,7 @@ void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4)
 {
 	outl(set1, ACPI_BASE_ADDRESS + GPE0_EN(GPE_31_0));
 	outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32));
-	outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_94_64));
+	outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_95_64));
 	outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
 }