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| author | Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> | 2025-04-10 10:47:22 +0800 |
|---|---|---|
| committer | Eric Lai <ericllai@google.com> | 2025-04-25 08:44:35 +0000 |
| commit | 7f8d1f208664424871fe1246030ed8b2ce622ff3 (patch) | |
| tree | 071f521427d45122f10b87ee7060ff81b10c7b4f /src | |
| parent | fe881c990c97354297473314c2d38941b96a1e89 (diff) | |
| download | coreboot-7f8d1f208664424871fe1246030ed8b2ce622ff3.tar.gz coreboot-7f8d1f208664424871fe1246030ed8b2ce622ff3.tar.bz2 coreboot-7f8d1f208664424871fe1246030ed8b2ce622ff3.zip | |
mb/google/nissa/var/pujjoniru: Support x32 memory configuration
Use GPP_E19 level to determine whether x32 memory configuration is
supported.
BUG=b:409144310
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I7c1f48f89186c3803e8e6a1bf163b824f2f06731
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87250
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Diffstat (limited to 'src')
4 files changed, 27 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 2bc0daaf94c9..73e908a75c82 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -498,6 +498,7 @@ config BOARD_GOOGLE_PUJJONIRU select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GFX_GENERIC select DRIVERS_AUDIO_SOF + select ENFORCE_MEM_CHANNEL_DISABLE select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD select SOC_INTEL_TWINLAKE diff --git a/src/mainboard/google/brya/variants/pujjoniru/Makefile.mk b/src/mainboard/google/brya/variants/pujjoniru/Makefile.mk index 4cf7fcace8ea..102ec17861c1 100644 --- a/src/mainboard/google/brya/variants/pujjoniru/Makefile.mk +++ b/src/mainboard/google/brya/variants/pujjoniru/Makefile.mk @@ -2,6 +2,7 @@ bootblock-y += gpio.c +romstage-y += memory.c romstage-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/pujjoniru/gpio.c b/src/mainboard/google/brya/variants/pujjoniru/gpio.c index 6845a6e9fd00..3fb85ed3b562 100644 --- a/src/mainboard/google/brya/variants/pujjoniru/gpio.c +++ b/src/mainboard/google/brya/variants/pujjoniru/gpio.c @@ -140,6 +140,9 @@ static const struct pad_config override_gpio_table[] = { /* C7 : SML1DATA ==> TCHSCR_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG), + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ /* BT_I2S_BCLK */ PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), @@ -178,6 +181,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG), }; static const struct pad_config romstage_gpio_table[] = { diff --git a/src/mainboard/google/brya/variants/pujjoniru/memory.c b/src/mainboard/google/brya/variants/pujjoniru/memory.c new file mode 100644 index 000000000000..51a7ff504cb5 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjoniru/memory.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +uint8_t mb_get_channel_disable_mask(void) +{ + /* + * GPP_E19 High -> One RAM Chip + * GPP_E19 Low -> Two RAM Chip + */ + if (gpio_get(GPP_E19)) { + /* Disable all other channels except first two on each controller */ + return (BIT(2) | BIT(3)); + } + + return 0; +} |