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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-06-23 21:21:51 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-06-29 21:51:50 +0000 |
| commit | 81bcce9c8d526cd772e26579c1458b00e53713d2 (patch) | |
| tree | 54e5cbcebc9534975f0e19852706f846a0e5be3a /src | |
| parent | c657ab9750dd040db2af9011d32c112bcdca8a5d (diff) | |
| download | coreboot-81bcce9c8d526cd772e26579c1458b00e53713d2.tar.gz coreboot-81bcce9c8d526cd772e26579c1458b00e53713d2.tar.bz2 coreboot-81bcce9c8d526cd772e26579c1458b00e53713d2.zip | |
soc/intel/common/irq: Add function to program north PCI IRQs
Because the FSP interface for PCI IRQs only includes the PCH devices,
this function is the complement to that, taking the list of irq entries,
and programming the PCI_INTERRUPT_LINE registers.
BUG=b:130217151, b:171580862, b:176858827
TEST=boot brya with patch train, verify with `lspci -vvv` that for all
the north PCI devices, their IRQ was either the one programmed by this
function, or an MSI was used.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I81cf7b25f115e41deb25767669b5466b5712b177
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55817
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/irq.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/irq/irq.c | 19 |
2 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/irq.h b/src/soc/intel/common/block/include/intelblocks/irq.h index 727020a5df7f..a0cb409ec806 100644 --- a/src/soc/intel/common/block/include/intelblocks/irq.h +++ b/src/soc/intel/common/block/include/intelblocks/irq.h @@ -46,4 +46,6 @@ const struct pci_irq_entry *assign_pci_irqs(const struct slot_irq_constraints *c void generate_pin_irq_map(const struct pci_irq_entry *entries); +void irq_program_non_pch(const struct pci_irq_entry *entries); + #endif /* SOC_INTEL_COMMON_IRQ_H */ diff --git a/src/soc/intel/common/block/irq/irq.c b/src/soc/intel/common/block/irq/irq.c index eb4daf9a147d..96fd733619d5 100644 --- a/src/soc/intel/common/block/irq/irq.c +++ b/src/soc/intel/common/block/irq/irq.c @@ -4,9 +4,11 @@ #include <console/console.h> #include <device/pci.h> #include <device/pci_def.h> +#include <device/pci_ops.h> #include <intelblocks/gpio.h> #include <intelblocks/irq.h> #include <intelblocks/lpc_lib.h> +#include <soc/pci_devs.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <stdlib.h> #include <string.h> @@ -394,3 +396,20 @@ void generate_pin_irq_map(const struct pci_irq_entry *entries) intel_write_pci0_PRT(pin_irq_map, map_count, &pirq_map); free(pin_irq_map); } + +void irq_program_non_pch(const struct pci_irq_entry *entries) +{ + while (entries) { + if (PCI_SLOT(entries->devfn) >= MIN_PCH_SLOT) { + entries = entries->next; + continue; + } + + if (entries->irq) + pci_s_write_config8(PCI_DEV(0, PCI_SLOT(entries->devfn), + PCI_FUNC(entries->devfn)), + PCI_INTERRUPT_LINE, entries->irq); + + entries = entries->next; + } +} |