soc/intel/skylake: Refactor memory layout calculation

This patch split entire memory layout calculation into
two parts. 1. Generic memory layout 2. SoC specific
reserve memory layout.

usable memory start = TOLUD - Generic memory size -
                   - soc specific reserve memory size.

Change-Id: I510d286ce5e0d8509ec31a65e971d5f19450364f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 157 insertions, 89 deletions

diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 6c640732cc33..0ade6916f53f 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -101,6 +101,126 @@ static bool is_ptt_enable(void)
 	return false;
 }
 
+/* Calculate PTT size */
+static size_t get_ptt_size(void)
+{
+	/* Allocate 4KB for PTT if enabled */
+	return is_ptt_enable() ? 4*KiB : 0;
+}
+
+/* Calculate Trace Hub size */
+static size_t get_tracehub_size(uintptr_t dram_base,
+		const struct soc_intel_skylake_config *config)
+{
+	uintptr_t tracehub_base = dram_base;
+	size_t tracehub_size = 0;
+
+	if (!config->ProbelessTrace)
+		return 0;
+
+	/* GDXC MOT */
+	tracehub_base -= GDXC_MOT_MEMORY_SIZE;
+	/* Round down to natual boundary accroding to PSMI size */
+	tracehub_base = ALIGN_DOWN(tracehub_base, PSMI_BUFFER_AREA_SIZE);
+	/* GDXC IOT */
+	tracehub_base -= GDXC_IOT_MEMORY_SIZE;
+	/* PSMI buffer area */
+	tracehub_base -= PSMI_BUFFER_AREA_SIZE;
+
+	/* Tracehub Area Size */
+	tracehub_size = dram_base - tracehub_base;
+
+	return tracehub_size;
+}
+
+/* Calculate PRMRR size based on user input PRMRR size and alignment */
+static size_t get_prmrr_size(uintptr_t dram_base,
+		const struct soc_intel_skylake_config *config)
+{
+	uintptr_t prmrr_base = dram_base;
+	size_t prmrr_size;
+
+	if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1))
+		prmrr_size = 1*MiB;
+	else
+		prmrr_size = config->PrmrrSize;
+
+	if (!prmrr_size)
+		return 0;
+
+	/*
+	 * PRMRR Sizes that are > 1MB and < 32MB are
+	 * not supported and will fail out.
+	 */
+	if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB))
+		die("PRMRR Sizes that are > 1MB and < 32MB are not"
+				"supported!\n");
+
+	prmrr_base -= prmrr_size;
+	if (prmrr_size >= 32*MiB)
+		prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB);
+
+	/* PRMRR Area Size */
+	prmrr_size = dram_base - prmrr_base;
+
+	return prmrr_size;
+}
+
+/* Calculate Intel Traditional Memory size based on GSM, DSM, TSEG and DPR. */
+static size_t calculate_traditional_mem_size(uintptr_t dram_base,
+		const struct device *dev)
+{
+	uintptr_t traditional_mem_base = dram_base;
+	size_t traditional_mem_size;
+
+	if (dev->enabled) {
+		/* Read BDSM from Host Bridge */
+		traditional_mem_base -= sa_get_dsm_size();
+
+		/* Read BGSM from Host Bridge */
+		traditional_mem_base -= sa_get_gsm_size();
+	}
+	/* Get TSEG size */
+	traditional_mem_base -= sa_get_tseg_size();
+
+	/* Get DPR size */
+	if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))
+		traditional_mem_base -= sa_get_dpr_size();
+
+	/* Traditional Area Size */
+	traditional_mem_size = dram_base - traditional_mem_base;
+
+	return traditional_mem_size;
+}
+
+/*
+ * Calculate Intel Reserved Memory size based on
+ * PRMRR size, Trace Hub config and PTT selection.
+ */
+static size_t calculate_reserved_mem_size(uintptr_t dram_base,
+		const struct device *dev)
+{
+	uintptr_t reserve_mem_base = dram_base;
+	size_t reserve_mem_size;
+	const struct soc_intel_skylake_config *config;
+
+	config = dev->chip_info;
+
+	/* Get PRMRR size */
+	reserve_mem_base -= get_prmrr_size(reserve_mem_base, config);
+
+	/* Get Tracehub size */
+	reserve_mem_base -= get_tracehub_size(reserve_mem_base, config);
+
+	/* Get PTT size */
+	reserve_mem_base -= get_ptt_size();
+
+	/* Traditional Area Size */
+	reserve_mem_size = dram_base - reserve_mem_base;
+
+	return reserve_mem_size;
+}
+
 /*
  * Host Memory Map:
  *
@@ -133,75 +253,55 @@ static bool is_ptt_enable(void)
  * the base registers from each other to determine sizes of the regions. In
  * other words, the memory map is in a fixed order no matter what.
  */
-static u32 calculate_dram_base(void)
+static uintptr_t calculate_dram_base(void)
 {
-	const struct soc_intel_skylake_config *config;
+	uintptr_t dram_base;
 	const struct device *dev;
-	uint32_t dram_base;
-	uint32_t prmrr_base;
-	size_t prmrr_size;
 
 	dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));
 	if (!dev)
-		die("ERROR - device not found!");
+		die("ERROR - IGD device not found!");
 
 	/* Read TOLUD from Host Bridge offset */
 	dram_base = sa_get_tolud_base();
 
-	if (dev->enabled) {
-		/* Read BDSM from Host Bridge */
-		dram_base -= sa_get_dsm_size();
+	/* Get Intel Traditional Memory Range Size */
+	dram_base -= calculate_traditional_mem_size(dram_base, dev);
 
-		/* Read BGSM from Host Bridge */
-		dram_base -= sa_get_gsm_size();
-	}
-	/* Get TSEG size */
-	dram_base -= sa_get_tseg_size();
-
-	/* Get DPR size */
-	if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))
-		dram_base -= sa_get_dpr_size();
-
-	config = dev->chip_info;
-	if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1))
-		prmrr_size = 1*MiB;
-	else
-		prmrr_size = config->PrmrrSize;
-
-	if (prmrr_size > 0) {
-		/*
-		 * PRMRR Sizes that are > 1MB and < 32MB are
-		 * not supported and will fail out.
-		 */
-		if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB))
-			die("PRMRR Sizes that are > 1MB and < 32MB are not"
-					"supported!\n");
-
-		prmrr_base = dram_base - prmrr_size;
-		if (prmrr_size >= 32*MiB)
-			prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB);
-		dram_base = prmrr_base;
-	}
-
-	if (config->ProbelessTrace) {
-		/* GDXC MOT */
-		dram_base -= GDXC_MOT_MEMORY_SIZE;
-		/* Round down to natual boundary accroding to PSMI size */
-		dram_base = ALIGN_DOWN(dram_base, PSMI_BUFFER_AREA_SIZE);
-		/* GDXC IOT */
-		dram_base -= GDXC_IOT_MEMORY_SIZE;
-		/* PSMI buffer area */
-		dram_base -= PSMI_BUFFER_AREA_SIZE;
-	}
-
-	if (is_ptt_enable())
-		dram_base -= 4*KiB; /* Allocate 4KB for PTT if enable */
+	/* Get Intel Reserved Memory Range Size */
+	dram_base -= calculate_reserved_mem_size(dram_base, dev);
 
 	return dram_base;
 }
 
-/* Get usable system memory start address */
-static u32 top_of_32bit_ram(void)
+/*
+ *     +-------------------------+  Top of RAM (aligned)
+ *     | System Management Mode  |
+ *     |      code and data      |  Length: CONFIG_TSEG_SIZE
+ *     |         (TSEG)          |
+ *     +-------------------------+  SMM base (aligned)
+ *     |                         |
+ *     | Chipset Reserved Memory |
+ *     |                         |
+ *     +-------------------------+  top_of_ram (aligned)
+ *     |                         |
+ *     |       CBMEM Root        |
+ *     |                         |
+ *     +-------------------------+
+ *     |                         |
+ *     |   FSP Reserved Memory   |
+ *     |                         |
+ *     +-------------------------+
+ *     |                         |
+ *     |  Various CBMEM Entries  |
+ *     |                         |
+ *     +-------------------------+  top_of_stack (8 byte aligned)
+ *     |                         |
+ *     |   stack (CBMEM Entry)   |
+ *     |                         |
+ *     +-------------------------+
+ */
+void *cbmem_top(void)
 {
 	/*
 	 * Check if Tseg has been initialized, we will use this as a flag
@@ -210,39 +310,7 @@ static u32 top_of_32bit_ram(void)
 	 * PRMRR_MASK MSR lock bit is set.
 	 */
 	if (sa_get_tseg_base() == 0)
-		return 0;
+		return NULL;
 
-	return calculate_dram_base();
-}
-
-void *cbmem_top(void)
-{
-	/*
-	 *     +-------------------------+  Top of RAM (aligned)
-	 *     | System Management Mode  |
-	 *     |      code and data      |  Length: CONFIG_TSEG_SIZE
-	 *     |         (TSEG)          |
-	 *     +-------------------------+  SMM base (aligned)
-	 *     |                         |
-	 *     | Chipset Reserved Memory |
-	 *     |                         |
-	 *     +-------------------------+  top_of_ram (aligned)
-	 *     |                         |
-	 *     |       CBMEM Root        |
-	 *     |                         |
-	 *     +-------------------------+
-	 *     |                         |
-	 *     |   FSP Reserved Memory   |
-	 *     |                         |
-	 *     +-------------------------+
-	 *     |                         |
-	 *     |  Various CBMEM Entries  |
-	 *     |                         |
-	 *     +-------------------------+  top_of_stack (8 byte aligned)
-	 *     |                         |
-	 *     |   stack (CBMEM Entry)   |
-	 *     |                         |
-	 *     +-------------------------+
-	 */
-	return (void *)top_of_32bit_ram();
+	return (void *)calculate_dram_base();
 }