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| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-22 18:34:51 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-01 18:15:33 +0000 |
| commit | 8308e2b9fa813e196b63eea02e54d77ab707652d (patch) | |
| tree | 917cb7b96432f58636ff7f3fcc6c2a63de341e4e /src | |
| parent | 68ab745086c6a062b5cb915424520bd0b18f7849 (diff) | |
| download | coreboot-8308e2b9fa813e196b63eea02e54d77ab707652d.tar.gz coreboot-8308e2b9fa813e196b63eea02e54d77ab707652d.tar.bz2 coreboot-8308e2b9fa813e196b63eea02e54d77ab707652d.zip | |
nb/intel/ironlake: Use `pci_update_config32()`
Change-Id: I7d36165e61e6399458479d47a33fe708eba7ea86
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/ironlake/early_init.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index acc76dabc686..4f221bfe9cce 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -63,8 +63,7 @@ static void early_cpu_init (void) /* bit 0 = disable multicore, bit 1 = disable quadcore, bit 8 = disable hyperthreading. */ - pci_write_config32(PCI_DEV(0xff, 0x00, 0), 0x80, - (pci_read_config32(PCI_DEV(0xff, 0x0, 0x0), 0x80) & 0xfffffefc) | 0x10000); + pci_update_config32(PCI_DEV(0xff, 0x00, 0), 0x80, 0xfffffefc, 0x10000); u8 reg8; struct cpuid_result result; |