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| author | Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> | 2021-08-27 00:01:46 +0530 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2022-08-01 19:00:20 +0000 |
| commit | 84753144d0d96ebe08c21d32c65b2fb8e31a18ba (patch) | |
| tree | f0addc1596ccbe388669e8146b4817a2c4aaf076 /src | |
| parent | 7a0440afc6d8aadb6208e16756b819a4a274b3bd (diff) | |
| download | coreboot-84753144d0d96ebe08c21d32c65b2fb8e31a18ba.tar.gz coreboot-84753144d0d96ebe08c21d32c65b2fb8e31a18ba.tar.bz2 coreboot-84753144d0d96ebe08c21d32c65b2fb8e31a18ba.zip | |
soc/qualcomm: Fill coreboot table with PCIe info
In order to pass PCIe base address to payloads, implement pcie_fill_lb()
to fill coreboot table with PCIe info.
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe endpoint
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: I1ca2be55b98c8d1b86576072078cdda02ac55940
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57614
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/qualcomm/common/pcie_common.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/qualcomm/common/pcie_common.c b/src/soc/qualcomm/common/pcie_common.c index 67f628287508..e27b0fcbfb02 100644 --- a/src/soc/qualcomm/common/pcie_common.c +++ b/src/soc/qualcomm/common/pcie_common.c @@ -410,6 +410,17 @@ static enum cb_err qcom_dw_pcie_enable(struct qcom_pcie_cntlr_t *pcie) return CB_SUCCESS; } +/** + * Fill coreboot table with PCIe info. + * It allows exporting this info to payloads. + */ +enum cb_err lb_fill_pcie(struct lb_pcie *pcie) +{ + pcie_cntlr_cfg_t *pcierc = qcom_pcie_cfg.cntlr_cfg; + pcie->ctrl_base = (uintptr_t)pcierc->dbi_base; + return CB_SUCCESS; +} + /* map_bus function for mapping pcie_s_{read/write}_configXX() functions */ volatile union pci_bank *pci_map_bus(pci_devfn_t dev) { |