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| author | Alexander Goncharov <chat@joursoir.net> | 2023-02-04 15:20:37 +0400 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2023-02-07 04:37:31 +0000 |
| commit | 893c3ae892961facc9be8bd300160222e694ab34 (patch) | |
| tree | ec628a8f9371fe96b783c7bf11dee59d065c0df5 /src | |
| parent | db4b71ff10b48624a1a0b76e3255bd206ef921d5 (diff) | |
| download | coreboot-893c3ae892961facc9be8bd300160222e694ab34.tar.gz coreboot-893c3ae892961facc9be8bd300160222e694ab34.tar.bz2 coreboot-893c3ae892961facc9be8bd300160222e694ab34.zip | |
tree: Drop repeated words
Found-by: linter
Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
30 files changed, 52 insertions, 52 deletions
diff --git a/src/Kconfig b/src/Kconfig index 8246a17a3e2c..16f788154f53 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -562,7 +562,7 @@ config CBFS_SIZE # Default value set at the end of the file help This is the part of the ROM actually managed by CBFS, located at the - end of the ROM (passed through cbfstool -o) on x86 and at at the start + end of the ROM (passed through cbfstool -o) on x86 and at the start of the ROM (passed through cbfstool -s) everywhere else. It defaults to span the whole ROM on all but Intel systems that use an Intel Firmware Descriptor. It can be overridden to make coreboot live alongside other diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index e332c3166348..f10b8a0367e6 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -192,7 +192,7 @@ static inline uint32_t read_clidr(void) return val; } -/* read cache size ID register register (CCSIDR) */ +/* read cache size ID register (CCSIDR) */ static inline uint32_t read_ccsidr(void) { uint32_t val = 0; diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 7e5817537ef5..1a7d8c6dd6f4 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -179,7 +179,7 @@ config X86_INIT_NEED_1_SIPI bool default n help - This option limits the number of SIPI signals sent during during the + This option limits the number of SIPI signals sent during the common AP setup. Intel documentation specifies an INIT SIPI SIPI sequence, however this doesn't work on some AMD and Intel platforms. These newer AMD and Intel platforms don't need the 10ms wait between @@ -197,7 +197,7 @@ config RESERVE_MTRRS_FOR_OS default n help This option allows a platform to reserve 2 MTRRs for the OS usage. - The Intel SDM documents that the the first 6 MTRRs are intended for + The Intel SDM documents that the first 6 MTRRs are intended for the system BIOS and the last 2 are to be reserved for OS usage. However, modern OSes use PAT to control cacheability instead of using MTRRs. diff --git a/src/include/device_tree.h b/src/include/device_tree.h index ae30c59710d7..02fcaa7234c3 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -91,10 +91,10 @@ struct device_tree * which were consumed reading the requested value. */ -/* Read the property, if any, at offset offset. */ +/* Read the property at offset, if any exists. */ int fdt_next_property(const void *blob, uint32_t offset, struct fdt_property *prop); -/* Read the name of the node, if any, at offset offset. */ +/* Read the name of the node at offset, if any exists. */ int fdt_node_name(const void *blob, uint32_t offset, const char **name); void fdt_print_node(const void *blob, uint32_t offset); diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 4b1b9af62c82..c408d5a4f65c 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -40,7 +40,7 @@ chip northbridge/intel/sandybridge device ref ehci2 on # USB2 EHCI #2 Unsupported PCI device 8086:1c2c subsystemid 0x8086 0x7270 end - device ref hda on # High Definition Audio Audio controller + device ref hda on # High Definition Audio controller subsystemid 0x8086 0x7270 end device ref pcie_rp1 on # PCIe Port #1 diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 163cdb33a9e5..b9f3f4d24cc0 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -57,7 +57,7 @@ chip northbridge/intel/sandybridge device ref ehci2 on # USB2 EHCI #2 subsystemid 0x1849 0x1e2d end - device ref hda on # High Definition Audio Audio controller + device ref hda on # High Definition Audio controller subsystemid 0x1849 0x8892 end device ref pcie_rp1 on # PCIe Port #1 diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb index 89ef4194b654..cb30fc3d1195 100644 --- a/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb @@ -5,7 +5,7 @@ chip northbridge/intel/sandybridge subsystemid 0x1043 0x844d inherit chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device pci 1b.0 on # High Definition Audio Audio controller + device pci 1b.0 on # High Definition Audio controller subsystemid 0x1043 0x8445 end device pci 1c.0 off end # PCIe Port #1 diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 98fcb629fe0a..bacdae86858d 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -11,7 +11,7 @@ static void bootblock_northbridge_init(void) { /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to + * setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final diff --git a/src/mainboard/google/dedede/smihandler.c b/src/mainboard/google/dedede/smihandler.c index 33c6b2ef53ac..7fc4c135a433 100644 --- a/src/mainboard/google/dedede/smihandler.c +++ b/src/mainboard/google/dedede/smihandler.c @@ -80,7 +80,7 @@ static void mainboard_config_cbi_wp(void) } /* - * Note that we are assuming that the Status Register protect bits are + * Note that we are assuming that the Status Register protect bits * are located at this index and that 1 means hardware protected. This * should be the case for these boards. */ diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 95d5368f529b..74c601a58f92 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -168,7 +168,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[2]" = "1" # RP 3, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[2]" = "1" - # RP 3 uses uses CLK SRC 0 + # RP 3 uses CLK SRC 0 register "PcieRpClkSrcNumber[2]" = "0" # Enable Root port 4(x1) for WLAN. @@ -181,7 +181,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[3]" = "1" # RP 4, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[3]" = "1" - # RP 4 uses uses CLK SRC 5 + # RP 4 uses CLK SRC 5 register "PcieRpClkSrcNumber[3]" = "5" # Enable Root port 5(x4) for NVMe. @@ -207,7 +207,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[8]" = "1" # RP 9, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[8]" = "1" - # RP 9 uses uses CLK SRC 2 + # RP 9 uses CLK SRC 2 register "PcieRpClkSrcNumber[8]" = "2" # Enable Root port 11 for BtoB. @@ -220,7 +220,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[10]" = "1" # RP 11, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[10]" = "1" - # RP 11 uses uses CLK SRC 2 + # RP 11 uses CLK SRC 2 register "PcieRpClkSrcNumber[10]" = "2" # Enable Root port 12 for BtoB. @@ -233,7 +233,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[11]" = "1" # RP 12, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[11]" = "1" - # RP 12 uses uses CLK SRC 2 + # RP 12 uses CLK SRC 2 register "PcieRpClkSrcNumber[11]" = "2" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 3ca1648e0fbf..07ed7bcae42c 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -10,7 +10,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[6]" = "1" # RP 7, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[6]" = "1" - # RP 7 uses uses CLK SRC 4 + # RP 7 uses CLK SRC 4 register "PcieRpClkSrcNumber[6]" = "4" # Enable Root port 8(x1) for TPU0 @@ -23,7 +23,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[7]" = "1" # RP 8, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[7]" = "1" - # RP 8 uses uses CLK SRC 2 + # RP 8 uses CLK SRC 2 register "PcieRpClkSrcNumber[7]" = "2" # Enable Root port 9(x4) for i350 LAN @@ -34,7 +34,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[8]" = "1" # RP 9, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[8]" = "1" - # RP 9 uses uses CLK SRC 2 + # RP 9 uses CLK SRC 2 register "PcieRpClkSrcNumber[8]" = "2" # These are part of Root port 9(x4) diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index d963d9df1f1f..2e3953ad4fe9 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -130,7 +130,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" - # RP 1 uses uses CLK SRC 1 + # RP 1 uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 25f75b8ffd23..07363fd0c5ff 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -135,7 +135,7 @@ chip soc/intel/skylake register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" - # RP 1 uses uses CLK SRC 1 + # RP 1 uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" # RP 1, Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 66c07db41f71..8be97c8c3620 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -133,7 +133,7 @@ chip soc/intel/skylake register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" - # RP 1 uses uses CLK SRC 1 + # RP 1 uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" # RP 1, Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 7cc3eb3029b4..a20c197537af 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -130,7 +130,7 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" - # RP 1 uses uses CLK SRC 1 + # RP 1 uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 13398d0dbed3..a18ec3c7797a 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -30,7 +30,7 @@ chip northbridge/intel/sandybridge device ref me_kt on end # Management Engine KT device ref gbe on end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on end # PCIe Port #1 device ref pcie_rp2 off end # PCIe Port #2 device ref pcie_rp3 off end # PCIe Port #3 diff --git a/src/mainboard/hp/z220_series/devicetree.cb b/src/mainboard/hp/z220_series/devicetree.cb index 265b0efd021b..71b186525419 100644 --- a/src/mainboard/hp/z220_series/devicetree.cb +++ b/src/mainboard/hp/z220_series/devicetree.cb @@ -34,7 +34,7 @@ chip northbridge/intel/sandybridge device ref me_kt on end # Management Engine KT device ref gbe on end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on end # PCIe Port #1 device ref pcie_rp2 off end # PCIe Port #2 device ref pcie_rp3 off end # PCIe Port #3 diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index df35e8a9f982..d5128140234b 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -10,37 +10,37 @@ chip soc/intel/skylake register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1 - # RP6, uses uses CLK SRC 1 + # RP6, uses CLK SRC 1 register "PcieRpClkSrcNumber[5]" = "1" register "PcieRpEnable[6]" = "1" register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2 - # RP7, uses uses CLK SRC 2 + # RP7, uses CLK SRC 2 register "PcieRpClkSrcNumber[6]" = "2" register "PcieRpEnable[7]" = "1" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 - # RP8, uses uses CLK SRC 3 + # RP8, uses CLK SRC 3 register "PcieRpClkSrcNumber[7]" = "3" register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 - # RP9, uses uses CLK SRC 4 + # RP9, uses CLK SRC 4 register "PcieRpClkSrcNumber[8]" = "4" register "PcieRpEnable[13]" = "1" register "PcieRpClkReqSupport[13]" = "1" register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5 - # RP14, uses uses CLK SRC 5 + # RP14, uses CLK SRC 5 register "PcieRpClkSrcNumber[13]" = "5" register "PcieRpEnable[16]" = "1" register "PcieRpClkReqSupport[16]" = "1" register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7 - # RP17, uses uses CLK SRC 7 + # RP17, uses CLK SRC 7 register "PcieRpClkSrcNumber[16]" = "7" # USB related diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index b1d291722be3..2c93a3892102 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -41,21 +41,21 @@ chip soc/intel/skylake register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "2" - # RP1, uses uses CLK SRC 2 + # RP1, uses CLK SRC 2 register "PcieRpClkSrcNumber[0]" = "2" # PCIE Port 5 x1 -> SLOT2/LAN register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" - # RP5, uses uses CLK SRC 3 + # RP5, uses CLK SRC 3 register "PcieRpClkSrcNumber[4]" = "3" # PCIE Port 6 x1 -> SLOT3 register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" - # RP6, uses uses CLK SRC 1 + # RP6, uses CLK SRC 1 register "PcieRpClkSrcNumber[5]" = "1" # PCIE Port 7 Disabled @@ -64,14 +64,14 @@ chip soc/intel/skylake register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" - # RP9, uses uses CLK SRC 5 + # RP9, uses CLK SRC 5 register "PcieRpClkSrcNumber[8]" = "5" # PCIE Port 10 x1 -> WiGig register "PcieRpEnable[9]" = "1" register "PcieRpClkReqSupport[9]" = "1" register "PcieRpClkReqNumber[9]" = "4" - # RP10, uses uses CLK SRC 4 + # RP10, uses CLK SRC 4 register "PcieRpClkSrcNumber[9]" = "4" # USB 2.0 Enable all ports diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 5c5382fbaaf1..23cbf96f40bb 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -101,15 +101,15 @@ chip soc/intel/skylake register "PcieRpClkReqNumber[5]" = "4" register "PcieRpClkReqNumber[8]" = "1" - # RP 3 uses uses CLK SRC 5# + # RP 3 uses CLK SRC 5# register "PcieRpClkSrcNumber[2]" = "5" - # RP 4 uses uses CLK SRC 2# + # RP 4 uses CLK SRC 2# register "PcieRpClkSrcNumber[3]" = "2" - # RP 5 uses uses CLK SRC 3# + # RP 5 uses CLK SRC 3# register "PcieRpClkSrcNumber[4]" = "3" - # RP 6 uses uses CLK SRC 4# + # RP 6 uses CLK SRC 4# register "PcieRpClkSrcNumber[5]" = "4" - # RP 9 uses uses CLK SRC 1# + # RP 9 uses CLK SRC 1# register "PcieRpClkSrcNumber[8]" = "1" # USB 2.0 Enable all ports diff --git a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb index fc00734b5e3c..fb05027d100b 100644 --- a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb +++ b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb @@ -41,7 +41,7 @@ chip northbridge/intel/haswell device pci 16.3 off end # Management Engine KT device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1b.0 on end # High Definition Audio controller device pci 1c.0 on end # PCIe Port #1, Realtek Card Reader device pci 1c.1 on # PCIe Port #2, WLAN smbios_slot_desc "0x14" "1" "M.2 2230" "8" diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index ca160945f2f5..a01274180058 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -41,7 +41,7 @@ chip northbridge/intel/sandybridge device ref me_kt off end # Management Engine KT device ref gbe off end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on end # PCIe Port #1 device ref pcie_rp2 on end # PCIe Port #2 device ref pcie_rp3 on end # PCIe Port #3 diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index f1054245d185..eae969633678 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -45,7 +45,7 @@ chip northbridge/intel/sandybridge device ref me_kt off end # Management Engine KT device ref gbe off end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on end # PCIe Port #1 device ref pcie_rp2 on end # PCIe Port #2 device ref pcie_rp3 off end # PCIe Port #3 diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index bcffdaa4e0a8..7e54383aa49c 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -43,7 +43,7 @@ chip northbridge/intel/sandybridge device ref me_kt off end # Management Engine KT device ref gbe on end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on # PCIe Port #1 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x87" diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 0acf98bbffc0..beb26095d488 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -55,7 +55,7 @@ chip northbridge/intel/sandybridge device ref me_kt off end # Management Engine KT device ref gbe off end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on end # PCIe Port #1 device ref pcie_rp2 on end # PCIe Port #2 (WLAN card) device ref pcie_rp3 on end # PCIe Port #3 (Card Reader) diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index c90c69c4f6d5..86e86f545517 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -96,7 +96,7 @@ chip soc/intel/alderlake }" register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING" - # Enable CPU PCIE RP 1, 2, 3 using using free running CLK (0x80) + # Enable CPU PCIE RP 1, 2, 3 using free running CLK (0x80) # Clock source is shared hence marked as free running. register "cpu_pcie_rp[CPU_RP(1)]" = "{ .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index c4a26955ba44..c0e9cb66485a 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -16,7 +16,7 @@ /* * Check Signature in EEPROM (M24C32-FMN6TP) - * If signature is there we assume that that the content is valid + * If signature is there we assume that the content is valid */ int check_signature(const size_t offset, const uint64_t signature) { diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 9866d55d7831..4a624e67cbca 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1111,7 +1111,7 @@ void cse_fw_sync(void) /* * If system is in recovery mode, CSE Lite update has to be skipped but CSE - * sub-partitions like NPHY and IOM have to to be updated. If CSE sub-parition update + * sub-partitions like NPHY and IOM have to be updated. If CSE sub-parition update * fails during recovery, just continue to boot. */ if (CONFIG(SOC_INTEL_CSE_SUB_PART_UPDATE) && vboot_recovery_mode_enabled()) { diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 7abb5bf3794a..0a4e03838587 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -47,8 +47,8 @@ static void lpc_init(struct device *dev) /* Disable LPC MSI Capability */ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); - byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is going - on on LPC, it holds PCI grant, so no LPC slave cycle can + byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is running + on LPC, it holds PCI grant, so no LPC slave cycle can interrupt and visit LPC. */ pci_write_config8(dev, 0x78, byte); diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c index d7817bdbe80b..e8a2f8014aff 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.c +++ b/src/vendorcode/eltan/security/mboot/mboot.c @@ -342,7 +342,7 @@ int __attribute__((weak))mb_measure(int wake_from_s3) * * mb_measure_log_start * - * performs the measurements defined by the the board routines. + * performs the measurements defined by the board routines. * * The logging is defined by the mb_log_list structure * |