diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-03-06 16:46:39 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-09 08:08:26 +0000 |
| commit | 9900cf80091ad1796c78c04b6ef6302410444480 (patch) | |
| tree | 9b67ea743db43287125b5635c0d85fafa2250645 /src | |
| parent | 7e303581bcda7d7a4a90d75a9b6f6698d55287ce (diff) | |
| download | coreboot-9900cf80091ad1796c78c04b6ef6302410444480.tar.gz coreboot-9900cf80091ad1796c78c04b6ef6302410444480.tar.bz2 coreboot-9900cf80091ad1796c78c04b6ef6302410444480.zip | |
mb/intel/tglrvp: Add memory config for Tiger Lake UP4
Add LPDDR4 memory configuration for Tiger Lake UP4 platform which
includes
1. DQ/DQs Mapping
2. Board id Support
3. SPD indexing
BUG=none
BRANCH=none
TEST= Build TGL UP4 successfully
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ibbd7036919c1a91ef12049d2af657f0a3597b57e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39365
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/tglrvp/board_id.h | 11 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/romstage_fsp_params.c | 9 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c | 34 |
3 files changed, 31 insertions, 23 deletions
diff --git a/src/mainboard/intel/tglrvp/board_id.h b/src/mainboard/intel/tglrvp/board_id.h index 364f4f7b04b5..8d0a31751b28 100644 --- a/src/mainboard/intel/tglrvp/board_id.h +++ b/src/mainboard/intel/tglrvp/board_id.h @@ -22,9 +22,14 @@ #define EC_FAB_ID_CMD 0x0D /* TGL-U Board IDs */ -#define TGL_U_LP4_SAMSUNG 0x3 -#define TGL_U_LP4_HYNIX 0xB -#define TGL_U_LP4_MICRON 0x13 +#define TGL_UP3_LP4_SAMSUNG 0x3 +#define TGL_UP3_LP4_HYNIX 0xB +#define TGL_UP3_LP4_MICRON 0x13 + +/* TGL-Y Board IDs */ +#define TGL_UP4_LP4_SAMSUNG 0x5 +#define TGL_UP4_LP4_HYNIX 0xD +#define TGL_UP4_LP4_MICRON 0x15 /* * Returns board information (board id[15:8] and diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index 89ae0ab3fba1..eb8fde0a6ad8 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -32,13 +32,16 @@ static uintptr_t mainboard_get_spd_index(void) printk(BIOS_INFO, "board id is 0x%x\n", board_id); switch (board_id) { - case TGL_U_LP4_MICRON: + case TGL_UP3_LP4_MICRON: + case TGL_UP4_LP4_MICRON: spd_index = SPD_ID_MICRON; break; - case TGL_U_LP4_SAMSUNG: + case TGL_UP3_LP4_SAMSUNG: + case TGL_UP4_LP4_SAMSUNG: spd_index = SPD_ID_SAMSUNG; break; - case TGL_U_LP4_HYNIX: + case TGL_UP3_LP4_HYNIX: + case TGL_UP4_LP4_HYNIX: spd_index = SPD_ID_HYNIX; break; default: diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c index 67979b649bd8..f3a8a48d45a5 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c @@ -25,28 +25,28 @@ size_t __weak variant_memory_sku(void) static const struct mb_lpddr4x_cfg mem_config = { /* DQ byte map */ .dq_map = { - { 0, 1, 6, 7, 3, 2, 5, 4, /* Byte 0 */ - 15, 8, 9, 14, 12, 11, 10, 13 }, /* Byte 1 */ - { 11, 12, 8, 15, 9, 14, 10, 13, /* Byte 2 */ - 3, 4, 7, 0, 6, 1, 5, 2 }, /* Byte 3 */ - { 4, 5, 3, 2, 7, 1, 0, 6, /* Byte 4 */ - 11, 10, 12, 13, 8, 9, 14, 15 }, /* Byte 5 */ - { 12, 11, 8, 13, 14, 15, 9, 10, /* Byte 6 */ - 4, 7, 3, 2, 1, 6, 0, 5 }, /* Byte 7 */ - { 11, 10, 9, 8, 12, 13, 15, 14, /* Byte 0 */ - 4, 5, 6, 7, 3, 2, 0, 1 }, /* Byte 1 */ - { 0, 7, 1, 6, 3, 5, 2, 4, /* Byte 2 */ - 9, 8, 10, 11, 14, 15, 13, 12 }, /* Byte 3 */ - { 4, 5, 6, 1, 3, 2, 7, 0, /* Byte 4 */ - 10, 13, 12, 11, 14, 9, 15, 8 }, /* Byte 5 */ - { 10, 12, 9, 15, 8, 11, 13, 14, /* Byte 6 */ - 3, 4, 1, 2, 6, 0, 5, 7 } /* Byte 7 */ + { 8, 9, 12, 11, 13, 15, 10, 14, /* Byte 0 */ + 4, 6, 0, 2, 5, 7, 1, 3 }, /* Byte 1 */ + { 2, 3, 0, 6, 1, 7, 5, 4, /* Byte 2 */ + 15, 14, 13, 8, 12, 11, 9, 10 }, /* Byte 3 */ + { 1, 0, 3, 2, 5, 4, 7, 6, /* Byte 4 */ + 14, 15, 12, 13, 8, 10, 9, 11 }, /* Byte 5 */ + { 8, 10, 11, 9, 15, 12, 14, 13, /* Byte 6 */ + 4, 7, 6, 5, 2, 0, 1, 3 }, /* Byte 7 */ + { 8, 9, 10, 11, 13, 12, 15, 14, /* Byte 0 */ + 7, 6, 4, 5, 0, 2, 1, 3 }, /* Byte 1 */ + { 1, 3, 0, 2, 6, 4, 5, 7, /* Byte 2 */ + 14, 15, 10, 12, 8, 13, 11, 9 }, /* Byte 3 */ + { 1, 0, 2, 4, 5, 3, 7, 6, /* Byte 4 */ + 12, 14, 15, 13, 9, 10, 8, 11 }, /* Byte 5 */ + { 11, 9, 8, 13, 12, 14, 15, 10, /* Byte 6 */ + 4, 7, 5, 1, 2, 6, 3, 0 } /* Byte 7 */ }, /* DQS CPU<>DRAM map */ .dqs_map = { /* Ch 0 1 2 3 */ - { 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 }, + { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 } }, |