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| author | Vincent Palatin <vpalatin@chromium.org> | 2018-03-12 14:04:01 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-14 11:18:47 +0000 |
| commit | 995d989ecbc7d17cf35ead1e5948b94eb22e1036 (patch) | |
| tree | 18c3d2055ae73456347bcc3033ae6a8577448b73 /src | |
| parent | 192afb6ad6a74b35dd952ef4cb7699c182682448 (diff) | |
| download | coreboot-995d989ecbc7d17cf35ead1e5948b94eb22e1036.tar.gz coreboot-995d989ecbc7d17cf35ead1e5948b94eb22e1036.tar.bz2 coreboot-995d989ecbc7d17cf35ead1e5948b94eb22e1036.zip | |
mb/google/zoombini/variants/meowth: Make FPMCU interrupt level-triggered
Fix the IRQ configuration: it must be level-sensitive not edge-sensitive
(and match the GPIO configuration).
BUG=b:71986991
BRANCH=none
TEST=on Meowth, /proc/interrupts shows 'IO-APIC 46-fasteoi chromeos-ec'
then run 'ectool --name=cros_fp fpmode fingerup' and see the number of
interrupts incrementing and the MKBP event happening.
Change-Id: Iba8cff21d637fe6bf4ef5152fc01aaf98906477d
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/25110
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/zoombini/variants/meowth/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index e49cc5db591a..062c6ecb7867 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -174,7 +174,7 @@ chip soc/intel/cannonlake register "hid" = "ACPI_DT_NAMESPACE_HID" register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A22_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A22_IRQ)" device spi 0 on end end end # GSPI #1 |