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| author | Huayang Duan <huayang.duan@mediatek.com> | 2020-02-21 12:00:15 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-06 08:00:29 +0000 |
| commit | 998737df71c3c2ed97da36305ef065eb280cf2b2 (patch) | |
| tree | a75fd0dc3171264e390446ba1cb5e9f251cbdfe1 /src | |
| parent | bb65180ee8b2cb26ac75fe6ccc9525ecc060c1e3 (diff) | |
| download | coreboot-998737df71c3c2ed97da36305ef065eb280cf2b2.tar.gz coreboot-998737df71c3c2ed97da36305ef065eb280cf2b2.tar.bz2 coreboot-998737df71c3c2ed97da36305ef065eb280cf2b2.zip | |
soc/mediatek/mt8183: Correct EMI bandwidth threshold for DVFS switch
Because eMCP and discrete DDR devices have different DVFS tables, their
EMI bandwidth thresholds should also be different. When the EMI total
bandwidth reaches the threshold, the system will notify DVFS module to
perform DVFS switch for system performance in low power states.
This patch increases the threshold from 0xa to 0xd for eMCP DDR devices
so that DVFS switch will be less likely to happen.
The register table of EMI_BWCT0 is incorrect in the datasheet. According
to the hardware design, BW_2ND_INT_BW_THR should be in bits [30:24]
instead of [22:16]. However, the logic in DRAM driver is correct,
aligned with the hardware design, so we don't need to correct it.
BRANCH=kukui
BUG=b:142358843
TEST=bootup pass
Change-Id: I82c3c70bcd90df3fdd613c0353aba0f176bc82bc
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39034
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/mediatek/mt8183/emi.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 07d1cc8ee5a9..e7cbda15d967 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -299,8 +299,10 @@ static void emi_init2(const struct sdram_params *params) setbits32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4); setbits32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4); - - write32(&emi_regs->bwct0, 0x0a000705); + if (CONFIG(MT8183_DRAM_EMCP)) + write32(&emi_regs->bwct0, 0x0d000705); + else + write32(&emi_regs->bwct0, 0x0a000705); write32(&emi_regs->bwct0_3rd, 0x0); /* EMI QoS 0.5 */ |